The counterflow pipeline processor architecture

Sproull, Robert F.; Sutherland, Ivan E.; Molnar, Charles E.

doi:10.1109/mdt.1994.303847

Cited by 115 publications

(53 citation statements)

References 5 publications

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“…By doing so, we can over-clock circuits to achieve higher throughput or scale down supply voltage for lower power consumption. Razor technique [4] is one of the most representative timing speculation techniques, which detects timing errors and conducts error recovery based on counterflow pipelining techniques [22]. During the error recovery phase, the pipeline is stopped for instruction replay.…”

Section: A Timing Speculationmentioning

confidence: 99%

Optimization for timing-speculated circuits by redundancy addition and removal

Liu

Yuan

et al. 2013

2013 18th Ieee European Test Symposium (Ets)

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Abstract-Integrated circuits suffer from severe variation effects with technology scaling, making their timing behavior increasingly unpredictable. Timing speculation is a promising technique to tackle this problem with the help of online timing error detection and correction mechanisms. In this paper, we propose to use redundancy addition and removal (RAR) technique to optimize timing-speculated circuits. By intentionally removing wires on those frequently-exercised critical paths and replacing them with wires on less critical ones (if possible), the proposed technique is able to greatly reduce the timing error rate of the circuit and improve its overall throughput, as shown in our experimental results on various benchmark circuits.

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Section: A Timing Speculationmentioning

confidence: 99%

Optimization for timing-speculated circuits by redundancy addition and removal

Liu

Yuan

et al. 2013

2013 18th Ieee European Test Symposium (Ets)

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“…This technique made it easier to implement operand forward, register renaming, and most importantly pipeline flushing [13,17]. In order to modify this technique for error recovery, a traditional pipeline is modified such that only the flush signals are bi-directional.…”

Section: Counterflow Pipeliningmentioning

confidence: 99%

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Crop

Krimer

Moezzi-Madani

et al. 2011

JLPEA

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While Moore's law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit J. Low Power Electron. Appl. 2011, 1 335 approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well.

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“…This period is exploited by each stage to re-compute its result using the correct data of the shadow latches. The second approach used in Razor is the counterflow pipelining which is based on the namesake processor architecture [12]. This technique is illustrated in Figure 4 and is characterized by negligible timing constraints in the pipeline operation at the expense of few cycles, depending on the pipeline depth, for error recovery.…”

Section: Ls2mentioning

confidence: 99%

Timing Error Detection and Correction by Time Dilation

Floros

Tsiatouhas

Kavousianos

2010

IFIP Advances in Information and Communication Technology

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Abstract. Timing failures in high complexity -high frequency integrated circuits, which are mainly caused by test escapes and environmental as well as operating conditions, are a real concern in nanometer technologies. The Time Dilation design technique supports both on-line (concurrent) error detection/correction and off-line scan testing. It is based on a new scan Flip-Flop and provides multiple error detection and correction at the minimum penalty of one clock cycle delay at the normal circuit operation for each error correction. No extra memory elements are required, like in earlier design approaches in the open literature, reducing drastically the silicon area overhead, while the performance degradation is negligible since no extra circuitry is inserted in the critical paths of a design.

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The counterflow pipeline processor architecture

Cited by 115 publications

References 5 publications

Optimization for timing-speculated circuits by redundancy addition and removal

Optimization for timing-speculated circuits by redundancy addition and removal

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Timing Error Detection and Correction by Time Dilation

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