The Cosyma System

Osterling, A.; Benner, Thomas; Ernst, Rolf; Herrmann, Dirk; Scholz, Thomas; Ye, Wei

doi:10.1007/978-1-4757-2649-7_8

Cited by 18 publications

(3 citation statements)

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“…Examples of such work include Polis [5], COSMOS [6], COSYMA [7], MOSES [8], Ptolemy [9], and SHE [10]. New tools for system-level design, design-space exploration, and verification have been the focus of academic research for several years.…”

Section: Available Solutionsmentioning

confidence: 99%

Early analysis tools for system-on-a-chip design

et al. 2002

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Section: Available Solutionsmentioning

confidence: 99%

Early analysis tools for system-on-a-chip design

et al. 2002

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“…. $10.00 platform template [15], [5] and considers the effects of platformimposed restrictions on system performance early in design process. However, these approaches require application recoding to accommodate the platform structure.…”

Section: Introductionmentioning

confidence: 99%

Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications

2010

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With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to-market projections, Transaction Level Modeling and Platform Aware Design are seen as promising approaches to efficient MPSoC design. In this paper, we present an automatized 3-phase process of Platform Aware Design and apply it to Kahn Process Networks (KPN) applications, a widely used model of computation for data-flow applications. We start with the KPN application and an abstract platform template and automatically generate an executable TLM with estimated timing that accurately reflects the system platform. We support homogeneous and heterogeneous multi-master platform models with shared memory or direct communication paradigm. The communication in heterogeneous platform modules is enabled with the transducer unit (TX) for protocol translation. TX units also act as message routers to support Network on Chip (NoC) communication. We evaluate our approach with the case study of the H.264 Encoder design process, in which the specification compliant design was reached from the KPN application in less than 2 hours. The example demonstrates that automatic generation of platform aware TLMs enables a fast, efficient and error resilient design process.

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“…Several design methods have been proposed to address the distribution of applications onto such heterogeneous processing platforms. Some approaches are based on the system simulation ( [1], [2], [3], [4], [5], [6]): The overall system is modeled in a high-level language for specification functional and performance validation, then decisions of hardware/software partitioning and bus architecture are based on quantitative results from simulation. These approaches enable the accurate evaluation of system architecture performance, but the development term of complex bus architecture modeling and the simulation performance of large system are critical issues.…”

Section: Introductionmentioning

confidence: 99%

A practical approach for bus architecture optimization at transaction level

Ogawa¹,

Noyer²,

Chauvet³

et al.

2003 Design, Automation and Test in Europe Conference and Exhibition

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For multimedia applications, the System LSI design trend is to integrate an increasing number of applications running on a single chip. Traditional architectures have reached their limit in terms of performance. New architectures must be explored to fulfill the system application needs. Complex bus structures have been introduced. These bus architectures open a much larger exploration space than traditional hardware-software partitioning trade-offs. We have been researching methods to leverage these new architectural elements. We also introduce a design environment to apply practical and efficient methods in today's design flow. Two key technologies are supporting our method and environment: Automatic bus architecture synthesis for easy configuration of bus architecture and transaction level of abstraction for communication for improvement of simulation performance. In this paper, we show the design method, an overview of the design environment and its usefulness through experimental results.

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The Cosyma System

Cited by 18 publications

References 0 publications

Early analysis tools for system-on-a-chip design

Early analysis tools for system-on-a-chip design

Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications

A practical approach for bus architecture optimization at transaction level

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