Early analysis tools for system-on-a-chip design

Darringer, John A.; Bergamaschi, Reinaldo A.; Bhattacharya, Subhrajit; Brand, Daniël; Herkersdorf, Andreas; Nair, Indira; Sagmeister, Patricia; Shin, Youngsoo

doi:10.1147/rd.466.0691

Cited by 31 publications

(13 citation statements)

References 10 publications

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“…The architecture for the IBM Network Processor have been obtained from [13,22]. The queueing models were built by using connectivity information from the architecture and the arrival rates of the requests were determined from the core graph [13] of the IBM Network Processor.…”

Section: Methodsmentioning

confidence: 99%

Applying stochastic modeling to bus arbitration for systems-on-chip

Kallakuri

Doboli

2007

Integration

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Section: Methodsmentioning

confidence: 99%

Applying stochastic modeling to bus arbitration for systems-on-chip

Kallakuri

Doboli

2007

Integration

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“…[11]) but not on the reverse process of synthesizing a performance model from a hardware design. However, the need for more automatic performance model synthesis from a design, especially for large system-onchip designs, is well-established [2]. Darringer, et al [2] recommend a top-down approach in which the system design is mapped into a performance model either at a low-level for accuracy or at a high-level in C++ for simulation speed.…”

Section: Related Workmentioning

confidence: 99%

Automatic performance model synthesis from hardware verification models

Bell

Cummings

Jackson

2011

Proceedings of the 2nd ACM/SPEC International Conference on Performance Engineering

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Performance models are typically written by hand for a new model or assembled piece-meal from the prior simulation code of an old model. In either case, many man-months of work may be required to write the new model and validate design details against a prior or current design. In reality, the majority of information about the performance of the design already exists in the design structure of either the old hardware model or the new model or both.To harvest this information and eliminate the significant duplicate coding and validation efforts, we propose that a performance model be automatically synthesized from a prior or current hardware design using a bottom-up, design-oriented approach. We demarcate the performance-critical boundaries of the design and perform backward-trace cone analysis to identify logic to include in the performance model. We then abstract specific components for design changes and expend modeling effort only on the few functions relevant to a particular design study. Engineering effort then becomes focused on workload selection and quality, defining and projecting new designs, and assessing design tradeoffs and sensitivities -the small set of tasks with the highest potential to improve design performance.We present a case-study that shows that even the simplest proposed transformations on a high-performance IBM L2 cache design result in a simulation speedup of 3.9, with evidence that an order of magnitude speedup can be obtained using a few additional modeling abstractions.

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“…Even in Register Transfer Level (RTL), it was almost impossible to port Real Time Operating System (RTOS) and do many different cases of architecture exploration in limited design time. Darringer et al [7] at IBM explained the method for architecture exploration and model validation. Even though they showed architecture exploration in many different areas, they were not able to achieve the accuracy or the simulation speed as we have.…”

Section: Introductionmentioning

confidence: 99%

Architecture Exploration for Performance Improvement of SoC Chip Based on AMBA System

Lee¹,

Yoon²

2007

2007 International Conference on Convergence Information Technology (ICCIT 2007)

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This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the project with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.2007 International Conference on Convergence Information Technology 0-7695-3038-9/07 $25.00

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Early analysis tools for system-on-a-chip design

Cited by 31 publications

References 10 publications

Applying stochastic modeling to bus arbitration for systems-on-chip

Applying stochastic modeling to bus arbitration for systems-on-chip

Automatic performance model synthesis from hardware verification models

Architecture Exploration for Performance Improvement of SoC Chip Based on AMBA System

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