The Compositional Specification of Timed Systems — A Tutorial

Sifakis, Joseph

doi:10.1007/3-540-48683-6_2

Cited by 12 publications

(15 citation statements)

References 12 publications

(3 reference statements)

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“…(4) The introduction of urgent transitions (or deadlines) in Uppaal, as advocated in Gebremichael and Vaandrager [2005], Sifakis [1999], and Sifakis and Yovine [1996]. This would allow us to eliminate the urgent channel urg, which is a modeling trick that is hard to explain to nonspecialists.…”

Section: Discussionmentioning

confidence: 99%

Formal specification and analysis of zeroconf using uppaalS

Berendsen

Gebremichael

Vaandrager

et al. 2011

ACM Trans. Embed. Comput. Syst.

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The model checker Uppaal is used to formally model and analyze parts of Zeroconf, a protocol for dynamic configuration of IPv4 link-local addresses that has been defined in RFC 3927 of the IETF. Our goal has been to construct a model that (a) is easy to understand by engineers, (b) comes as close as possible to the informal text (for each transition in the model there should be a corresponding piece of text in the RFC), and (c) may serve as a basis for formal verification. Our modeling efforts revealed several errors (or at least ambiguities) in the RFC that no one else spotted before. We present two proofs of the mutual exclusion property for Zeroconf (for an arbitrary number of hosts and IP addresses): a manual, operational proof, and a proof that combines model checking with the application of a new abstraction relation that is compositional with respect to committed locations. The model checking problem has been solved using Uppaal and the abstractions have been checked by hand.

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Section: Discussionmentioning

confidence: 99%

Formal specification and analysis of zeroconf using uppaalS

Berendsen

Gebremichael

Vaandrager

et al. 2011

ACM Trans. Embed. Comput. Syst.

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“…Similar to our work, some other real-time formalisms have been translated or projected to other formalisms for model-checking [29], [23]. This work is also related to works on compositional modeling of real-time systems [4], [3], [41], [22] and works on specification patterns in general [18], [30].…”

mentioning

confidence: 82%

Timed Automata Patterns

Dong

Peng

Qin

et al. 2008

IIEEE Trans. Software Eng.

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The full-text may be used and/or reproduced, and given to third parties in any format or medium, without prior permission or charge, for personal research or study, educational, or not-for-prot purposes provided that: • a full bibliographic reference is made to the original source • a link is made to the metadata record in DRO • the full-text is not changed in any way The full-text must not be sold in any format or medium without the formal permission of the copyright holders.

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“…Compositional specification for real-time systems based on timed process algebras has been studied extensively. Examples include the algebra of timed processes named ATP [Sifakis 1999;Nicollin and Sifakis 1994], the extension of CCS with real time [Yi 1991] and Timed CSP [Reed and Roscoe 1986;Schneider 2000]. Stateful Timed CSP is an extension of Timed CSP.…”

Section: Related Workmentioning

confidence: 99%

Modeling and verifying hierarchical real-time systems using stateful timed CSP

Sun

Liu

Dong

et al. 2013

ACM Trans. Softw. Eng. Methodol.

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Modeling and verifying complex real-time systems are challenging research problems. The de facto approach is based on Timed Automata, which are finite state automata equipped with clock variables. Timed Automata are deficient in modeling hierarchical complex systems. In this work, we propose a language called Stateful Timed CSP and an automated approach for verifying Stateful Timed CSP models. Stateful Timed CSP is based on Timed CSP and is capable of specifying hierarchical real-time systems. Through dynamic zone abstraction, finite-state zone graphs can be generated automatically from Stateful Timed CSP models, which are subject to model checking. Like Timed Automata, Stateful Timed CSP models suffer from Zeno runs, that is, system runs that take infinitely many steps within finite time. Unlike Timed Automata, model checking with non-Zenoness in Stateful Timed CSP can be achieved based on the zone graphs. We extend the PAT model checker to support system modeling and verification using Stateful Timed CSP and show its usability/scalability via verification of real-world systems.

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The Compositional Specification of Timed Systems — A Tutorial

Cited by 12 publications

References 12 publications

Formal specification and analysis of zeroconf using uppaalS

Formal specification and analysis of zeroconf using uppaalS

Timed Automata Patterns

Modeling and verifying hierarchical real-time systems using stateful timed CSP

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