The Characterization of InAlN/AlN/GaN HEMTs Using Silicon-on-Insulator (SOI) Substrate Technology

Abstract

The microwave and low frequency noise characteristics of 6 inch InAlN/AlN/GaN high electron mobility transistor (HEMT) were demonstrated and investigated on silicon-on-insulator (SOI) substrate for the first time. The InAlN HEMT on SOI substrate was grown by metal organic chemical vapor deposition (MOCVD) on a p-type (111) Si SOI substrate with a p-type (100) Si handle wafer for possible heterogeneous integration. The Raman spectroscopy measurement indicates that the smaller epitaxy stress was obtained by adopting SOI wafer and X-ray diffraction measurements revealed that InAIN HEMT on SOI achieves a flat surface and an abrupt heterointerface. The InAlN HEMT on SOI exhibits a lower leakage current compared to the device on high resistivity (HR) Si substrate and thus improves the off-state breakdown voltage from 134 V to 198 V. Moreover, the buried SiO2 in SOI substrate also efficiently suppresses the signal loss resulting in the better bandwidth and the microwave power performance. Based on the low frequency noise measurement, InAlN HEMT on SOI substrate also performs a relatively slight degradation after hot carrier stress.

Improved Off-State Leakage Current and Cutoff Frequency for AlGaN/GaN HEMT by Using Silicon-on-Insulator

“…This work represents a significant improvement in Ion/Ioff ratio and cutoff frequency on SOI substrates as compared with the reported values. 10,12,24,25 However, the lower values of f t × L g and f max × L g could be due to the without deembedded measurements and the low thermal conductivity of silicon substrate that limits the performance of GaN HEMT at a smaller gate length. The improvement of f max for GaN HEMT/SOI device can be achieved by introducing the trap rich layer 26,27 or removing the base silicon substrate.…”

“…Attention was also extended to SOI substrates for their low parasitic capacitance and high speed 9 to develop GaN HEMT devices with AlGaN/GaN, 10,11 InAlN/AlN/GaN heterostructures 12 and enhancement-mode p-GaN HEMTs. 13 The GaN grown on SOI showed remarkably improved GaN stress, leakage current, and breakdown voltage compared to the traditional silicon substrate.…”

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

“…This implies that by heavily doping in handle wafer not only reduce the bowing effect, but also improve the quality of substrate and the performance of high-power device. GaN-on-SOI substrate exhibits a capability to improve the power device performance and also have been proven by many research teams [168][169][170][171][172] including smaller reverse recovery leakage [169], higher breakdown voltage [168,169] and smaller vertical leakage [172]. Kevin J. Chen et al [169] reported the SOI substrate with a reduced stress in the GaN epilayers (shown as Figure 18a) and an excellent E-mode HEMTs on SOI produced by fluorine plasma implantation method with a high ON/OFF current ratio (10 8 -10 9 ), large breakdown voltage (1471 V with floating substrate), and also a smaller vertical leakage at reverse bias, as shown in Figure 18b.…”

“…SOI substrate is outstanding for its better vertical isolation performance and a lower substrate loss [183]. Besides, when compared to GaN on Si substrate devices, GaN on SOI substrate devices demonstrated better DC, breakdown voltage, and RF properties [170,184,185]. It was demonstrated that GaN-on-SOI substrates perform better in terms of tensile stress relaxation and surface flatness than Si substrates.…”

MOVPE growth of GaN on 6-inch SOI-substrates: effect of substrate parameters on layer quality and strain

“…This buried oxide (BOX) can improve the breakdown characteristics of these devices, and thus, help to propel GaN on Si powerelectronics to higher operating voltage ranges. Furthermore, in high frequency applications, the insulating BOX layer could reduce the losses and crosstalk caused by the conducting Si substrate [12]. However, the use of a SOI substrate can increase the thermal stresses during epitaxy and lead to cracks in the GaN layer or, in extreme cases, cracks in the SOI device Si layer [11,13].…”