The Characterization and Passivation of Fixed Oxide Charges and Interface States in the $\hbox{Al}_{2}\hbox{O}_{3}/ \hbox{InGaAs}$ MOS System

Abstract

In this paper, we present a review of experimental results examining charged defect components in the Al 2 O 3 / In 0.53 Ga 0.47 As metal-oxide-semiconductor (MOS) system. For the analysis of fixed oxide charge and interface state density, an approach is described where the flatband voltage for n-and p-type Al 2 O 3 /In 0.53 Ga 0.47 As MOS structures is used to separate and quantify the contributions of fixed oxide charge and interface state density. Based on an Al 2 O 3 thickness series (10-20 nm) for the n-and p-type In 0.53 Ga 0.47 As layers, the analysis reveals a positive fixed charge density (∼ 9 × 10 18 cm −3 ) distributed throughout the Al 2 O 3 and a negative sheet charge density (−8 × 10 12 cm −2 ) located near the Al 2 O 3 /In 0.53 Ga 0.47 As interface. The interface state density integrated across the energy gap is ∼1 × 10 13 cm −2 and is a donor-type (+/0) defect. The density of the fixed oxide charge components is significantly reduced by forming gas (5% H 2 /95%N 2 ambient at 350 • C for 30 minutes) annealing. The interface state distribution obtained from multifrequency capacitance-voltage and conductance-voltage measurements on either MOS structures or MOSFETs indicates a peak density located around the In 0.53 Ga 0.47 As midgap energy, with a sharp increase in the interface state density toward the valance band and evidence of interface states aligned with the In 0.53 Ga 0.47 As conduction band. The integrated interface state density obtained from multi-frequency capacitance-voltage and conductance-voltage analysis is in good agreement with the approach of comparing the flatband voltages in n-and p-type Al 2 O 3 /In 0.53 Ga 0.47 As MOS structures. Finally, this Manuscript paper reviews recent work based on an optimization of the In 0.53 Ga 0.47 As surface preparation using (NH 4 ) 2 S, combined with minimizing the transfer time to the atomic layer deposition reactor for Al 2 O 3 , which indicates interface state reduction (< 10 12 cm −2 eV −1 ) and genuine surface inversion for both n-and p-type Al 2 O 3 /In 0.53 Ga 0.47 As MOS structures.

Accumulation capacitance frequency dispersion of III-V metal-insulator-semiconductor devices due to disorder induced gap states

“…5 shows C total in accumulation as a function of measurement frequency for our experimental results as well as similar results from the literature. 15,[31][32][33][34] The change in total accumulation capacitance from the lowest to highest measurement frequency for our results is largely consistent with those of the literature. We note that while the substrates and dielectrics used for our comparisons are the same, many of the experimental conditions (e.g., oxide thickness, pre-treatments, annealing conditions) are different.…”

Effect of forming gas annealing on the inversion response and minority carrier generation lifetime of n and p-In0.53Ga0.47As MOS capacitors

“…By contrast, for the two thicker Al 2 O 3 layers, 8 nm and 12 nm Al 2 O 3 on both n-and p-In 0.53 Ga 0.47 As, the removal of fixed positive charge is observed after the anneal. Some previous reports on ALD Al 2 O 3 films on In 0.53 Ga 0.47 As [10,11], and on GaSb [12] have indicated the presence of negative fixed charges in proximity to the Al 2 O 3 -semiconductor interface, and positive fixed charges distributed throughout the Al 2 O 3 film. This is in agreement with the results in this work where for the 4 nm films the negative fixed charge is dominant, and for thicker films the positive fixed charge dominates, with the FGA treatment reducing the fixed charge components in both cases.…”

(Invited) Towards a Vertical and Damage Free Post-Etch InGaAs Fin Profile: Dry Etch Processing, Sidewall Damage Assessment and Mitigation Options

“…Our concern here is the extent of electrical damage to the dielectric/sidewall interface. In MOS technology, the electrical properties at the dielectric/semiconductor interface are routinely studied from capacitancevoltage (C-V) characteristics derived from MOSCAPs (6)(7)(8). On the basis of this, the impact of the etch processes on the electrical properties of the sidewall MOS interface is assessed from MOSCAP measurements in this work.…”