2010
DOI: 10.1149/1.3483536
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The Characteristics of Interface Microstructures in Germanium/SiO2 Low Temperature Wafer Bonding

Abstract: Ge/SiO 2 direct wafer bonding by O 2 -plasma pretreatment was investigated. The bonding interfaces of Ge/SiO 2 low temperature direct wafer bonding were characterized by transmission electron microscopy. The perfectly atomic level Ge/SiO 2 bonding was achieved after a 150 0 C annealing for 60 hours. The excessive O 2 -plasma exposure resulted in micro-crack formation close to the bonding interface in Ge. A model involved micro-crack formed in Ge was proposed. Our experiments, for the first time, demonstrated t… Show more

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Cited by 4 publications
(8 citation statements)
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“…It is important to perform the Smart-cut process in which strong bonding strength has to obtain in ahead of surface exfoliation because atomic level wafer bonding of Ge/Si with 300 nm oxide can be accomplished by 150 • C annealing for 60 hours. 23 In the investigation, 24 it was found that the blistering occurred immediately without any annealing for more than 5 × 10 16 cm −2 H-implanted dose in room temperature with low energy (5 KeV). The blistering of as-implanted sample was not viewed in our works for both 5 × 10 16 cm −2 and 1 × 10 17 cm −2 doses.…”
Section: Resultsmentioning
confidence: 96%
“…It is important to perform the Smart-cut process in which strong bonding strength has to obtain in ahead of surface exfoliation because atomic level wafer bonding of Ge/Si with 300 nm oxide can be accomplished by 150 • C annealing for 60 hours. 23 In the investigation, 24 it was found that the blistering occurred immediately without any annealing for more than 5 × 10 16 cm −2 H-implanted dose in room temperature with low energy (5 KeV). The blistering of as-implanted sample was not viewed in our works for both 5 × 10 16 cm −2 and 1 × 10 17 cm −2 doses.…”
Section: Resultsmentioning
confidence: 96%
“…There are two methods for successful bonding of Ge onto a substrate (Figure ): (1) direct bonding of a Ge wafer with a substrate, commonly a Si substrate, and (2) anodic bonding of a Ge wafer, usually with a glass substrate. However, these studies concerned Ge wafer bonding without Ge wafer thinning or polishing. As this work is aimed at LEDs or lasers made of Ge thin films, thinning Ge to micrometer thickness is required, which can be done by a wet etch method .…”
Section: Methodsmentioning
confidence: 99%
“…In the direct bonding of Ge on Si, an interlayer such as SiO 2 or Al 2 O 3 is needed to bond the two wafers. The two wafers were connected with the hydroxyl groups at the interface where the van der Waals force bonded the wafer together .…”
Section: Methodsmentioning
confidence: 99%
“…In order to minimize the ion channeling effect during implantation, the sample surface normal was inclined at ~7°. After implantation the wafers were cut into small pieces (5×5 mm 2 ) and subsequently annealed in the low temperature range (200-250 0 C for 1×10 17 cm -2 and 250-350 0 C for 3×10 16 cm -2 and 5×10 16 cm -2 ) in ambient atmosphere, it was worth noting that samples were loaded into the furnace at room temperature and then heated by a ramping up at the rate of 2 0 C/min for annealing through different temperatures and durations to fit the practical Smart-cut process and reduce the stress from the difference of thermal expansion coefficients in the future heterogeneous material integration by means of wafer bonding. It must be noted that the ramp-up rate was employed at a rate of 0.5 0 C/min for germanium surface blistering and for wafer bonding in the literature (6).…”
Section: Methodsmentioning
confidence: 99%
“…However, the process of the heterogeneous wafer bonding has to be carried out under the low temperature to avoid the bonded pair crack thanks to the difference of thermal expansion coefficient between both dissimilar materials. The atomic level Ge/SiO 2 wafer bonding has been demonstrated by 150 0 C annealing in our previous report (16) but the resolution from the infrared imaging of wafer bonding interface is limited. In this paper, we report a low temperature Smart-cut process for GeOI fabrication (i.e.…”
Section: Introductionmentioning
confidence: 99%