The challenge of signal integrity in deep-submicrometer CMOS technology

Caignet, Fabrice; Delmas-Bendhia, S.; Sicard, Étienne

doi:10.1109/5.920583

Cited by 129 publications

(42 citation statements)

References 25 publications

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“…Nourani and Attarha [2001] presented two ILS cell designs to detect voltage distortions and timing violations, respectively. Later, several other ILS designs [Caignet et al 2001;Tabatabaei and Ivanov 2002] were introduced, which are more accurate in measuring voltage and/or timing violations, at the cost of large area overheads. Assuming the existence of logic BIST structures in an SOC, Sekhar and Dey [2002] presented a self-test solution, called LI-BIST, for both the core internal logic and the SOC interconnects.…”

Section: Related Work and Motivationmentioning

confidence: 99%

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Zhang

Chakrabarty

2009

ACM Trans. Des. Autom. Electron. Syst.

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The test time for core-external interconnect shorts and opens is typically much less than that for core-internal logic. Therefore, prior work on test-infrastructure design for core-based system-ona-chip (SOC) has mainly focused on minimizing the test time for core-internal logic. However, as feature sizes shrink for newer process technologies, the test time for signal integrity (SI) faults on interconnects cannot be neglected. The test time for SI faults can be comparable to, or even larger than, the test time for the embedded cores. We investigate the impact of interconnect SI tests on SOC test-architecture design and optimization. A compaction method for SI faults and algorithms for test-architecture optimization are also presented. Experimental results for the ITC'02 benchmarks show that the proposed approach can significantly reduce the overall testing time for core-internal logic and core-external interconnects.

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Section: Related Work and Motivationmentioning

confidence: 99%

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Zhang

Chakrabarty

2009

ACM Trans. Des. Autom. Electron. Syst.

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“…Two major radiation effects should be mentioned: the total cumulative dose called Total Ionizing Dose (TID) which is related to interactions between the semiconductor and the trapped particles, and transient events called Single Event Effects (SEE) resulting from high energy particles and random occurrences [7], [8]. Nowadays, instead of using technologies dedicated to space (such as specific BiCMOS or SOI) in order to improve the radiation hardness of integrated circuits, it seems appropriate to use specific design techniques (radiation hardening by design (RHBD)) [7], [9] applied on standard CMOS technologies which are less expensive [10], provide higher performances and for which parasitic effects are studied and well known [11], [12]. The choice of the technology depends first on the duration of the mission as well as on the radiative environments which is related to the space probe orbit trajectory.…”

Section: Introductionmentioning

confidence: 99%

Low Noise CMOS Analog Front-End Circuit With an 8-bit 1-MS/s ADC for Silicon Sensors for Space Applications

et al. 2014

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A low power analog front-end circuit for silicon (Si) detectors has been fabricated in 0.35 µm CMOS technology. It has been designed to read out signals from large-capacitance Si detectors for incident electron energy ranging from 50 keV to 725 keV. In order to quantify electron energy, the front-end integrates a charge preamplifier, a pulse shaper, a peak detector and an event-driven analog-to-digital converter (ADC). The complete front end including the ADC dissipates 2.5 mW for a maximum electron detecting rate of 650 kHz. The charge-to-voltage gain is approximately 60 mV/fC for a charge range of 0.6 fF to 32 fF. The measured equivalent noise charge (ENC) is 3119 e − for a 40 pF detector parasitic capacitance. Index TermsSi Detector, Charge preamplifier, electron energy measurement.

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“…Performance is mainly limited by interconnect in deep submicron [2]. Hence, it is important to investigate and optimize the performance of interconnects in sub threshold application domain.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of SWCNTS Bundles and MWCNT Interconnects for Subthreshold Circuits

Kumar¹

2014

IJRET

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The challenge of signal integrity in deep-submicrometer CMOS technology

Cited by 129 publications

References 25 publications

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Low Noise CMOS Analog Front-End Circuit With an 8-bit 1-MS/s ADC for Silicon Sensors for Space Applications

Performance Analysis of SWCNTS Bundles and MWCNT Interconnects for Subthreshold Circuits

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