“…This will result in a complete solution that deals with the design, as well as the testing of a system. This approach is contrary to the approaches described in [1,2,8,10,13,28], where the authors only present partial solutions. Embodied within SIERA is a test environment that fulfills the above requirements, where the designer, has available, hardware modules at both the chip and board level that implement Scan Path [5,6,24], Built-In-Self-Test (BIST) [19,25], and the Boundary Scan architecture [9,18], as well as, software tools for connecting these modules together, test languages that describe what DFT modules are used and how to use them during test, and a software programmable custom controller board that is used to control and access the devices (chips and boards) which contain this hardware.…”