Proceedings. International Test Conference 1990
DOI: 10.1109/test.1990.114037
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The boundary-scan master: target applications and functional requirements

Abstract: The IEEE Std. 1149.1Boundary-Scan Architecture [l] relies on the serial test access port (TAP) for communicating with the unitunder-test @JUT). The UUT can be a simple device, a printed-circuit board, or a complex system. Since it is cumbersome and inefficient for a test and diagnostic processor to directly communicate with the UUT via the serial TAP, we have developed the Boundary-Scan Master chip (BSM) for simplifying the parallel-serial interface.This paper describes several applications of the BSM aimed a… Show more

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Cited by 24 publications
(3 citation statements)
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“…Several IEEE 1149.1 test controller solutions have been developed over the years [12]- [17], but little attention has been given to controller architectures proposed as embedded coprocessors. The work described in this paper offers two main contributions with this respect, by proposing:…”
Section: Discussionmentioning
confidence: 99%
“…Several IEEE 1149.1 test controller solutions have been developed over the years [12]- [17], but little attention has been given to controller architectures proposed as embedded coprocessors. The work described in this paper offers two main contributions with this respect, by proposing:…”
Section: Discussionmentioning
confidence: 99%
“…This will result in a complete solution that deals with the design, as well as the testing of a system. This approach is contrary to the approaches described in [1,2,8,10,13,28], where the authors only present partial solutions. Embodied within SIERA is a test environment that fulfills the above requirements, where the designer, has available, hardware modules at both the chip and board level that implement Scan Path [5,6,24], Built-In-Self-Test (BIST) [19,25], and the Boundary Scan architecture [9,18], as well as, software tools for connecting these modules together, test languages that describe what DFT modules are used and how to use them during test, and a software programmable custom controller board that is used to control and access the devices (chips and boards) which contain this hardware.…”
Section: The Siera Design Environmentmentioning
confidence: 92%
“…Scan Protocol Support: An option was considered to include a "master" TAP Controller and control TMS directly in hardware. ICs have been presented that implement this kind of serial port controller 4,5 . With this method, scan operations can be controlled by issuing a predefined set of commands.…”
Section: Technologymentioning
confidence: 99%