The Best Flip-Flops to Scan

Abramovici, M.; Kulikowski, J. J.; Roy, Ranjan

doi:10.1109/test.1991.519507

Cited by 75 publications

(17 citation statements)

References 15 publications

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“…Transitions at the output of unblockable gates cannot be blocked by assigning any combination of binary values to primary inputs. Uncontrollable gates are identified by performing uncontrollability analysis [13]. The analysis starts by assigning all scan inputs to , where the assignment of assigned to a line denotes that the line is uncontrollable to 1 (0) [13].…”

Section: ) Expanding the Definition Of Conflict-free Assignmentmentioning

confidence: 99%

“…Uncontrollable gates are identified by performing uncontrollability analysis [13]. The analysis starts by assigning all scan inputs to , where the assignment of assigned to a line denotes that the line is uncontrollable to 1 (0) [13]. Next these values are propagated to all internal lines according to the propagation rules defined in [13].…”

Section: ) Expanding the Definition Of Conflict-free Assignmentmentioning

confidence: 99%

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An automatic test pattern generator for minimizing switching activity during scan testing activity

Wang

Gupta

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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An automatic test pattern generation (ATPG) technique is proposed that reduces switching activity during testing of sequential circuits that have full scan. The objective is to permit safe and inexpensive testing of low-power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speed. The approach works with standard scan designs that are commonly used and typically have significantly lower overhead than enhanced scan designs. The proposed ATPG exploits all possible "don't cares" that occur during scan shifting, test application, and response capture to minimize switching activity in the circuit under test. An ATPG that minimizes the number of state inputs that are assigned specific binary values has been developed. Don't cares at state inputs are assigned binary values that cause the minimum number of transitions during scan shifting and don't cares at primary inputs during scan shifting and capture are used to block gates that may have transitions during scan shifting. The proposed technique has been implemented and the generated tests are compared with those generated by a simple PODEM implementation for full scan versions of ISCAS89 benchmark circuits. Tests generated by the proposed ATPG decrease the average number of transitions during test by between 11% and 99%, with higher reductions occurring in circuits that have larger numbers of primary and state inputs. Further experiments demonstrate that the proposed ATPG generates tests that provide significantly greater reductions in switching activity than previous approaches for achieving the same objective and have the added advantage of being scalable for large circuits.

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Section: ) Expanding the Definition Of Conflict-free Assignmentmentioning

confidence: 99%

Section: ) Expanding the Definition Of Conflict-free Assignmentmentioning

confidence: 99%

An automatic test pattern generator for minimizing switching activity during scan testing activity

Wang

Gupta

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…For every stem s, FIRE determines the sets of faults S 0 and S 1 , which require, respectively, s = 0 and s = 1 as necessary conditions for their detection. This is accomplished using an improved version of the uncontrollability and unobservability analysis proposed in [22] . In this analysis, 0 (1) denotes the status of a line that is uncontrollable for value 0 (1).…”

Section: The Combinational Fire Algorithmmentioning

confidence: 99%

Identifying sequential redundancies without search

Iyer

Long²,

Abramovici³

1996

Proceedings of the 33rd Annual Conference on Design Automation Conference - DAC '96

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“…Because the conditions for S x , S y and S z cannot be satisfied simultaneously, faults in S xyz = S x T S y T S z are redundant. The faults that belong to S x can be found by uncontrollability and unobservability analysis [1,2,3]. Let 0(1) denote the status of a line that is uncontrollable to value 0(1).…”

Section: Identifying Combinational Redundancymentioning

confidence: 99%