The Balance multiprocessor system

Thakkar, Shreekant; Gifford, P.; Fielland, G.N.

doi:10.1109/40.521

Cited by 35 publications

(9 citation statements)

References 5 publications

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“…For microprocessors and multi-core chips, low-and high-level memory models have arguably taken (at least) three decades to mature. Microprocessors emerged in 1971 for uniprocessors and were also put in multiprocessors in the early 1980's (e.g., Sequent Balance [37]). Even though Lamport [24] specified sequential consistency (SC) in 1979, most multiprocessors do not implement SC due to their use of write buffers.…”

Section: Memory Consistency Modelsmentioning

confidence: 99%

Heterogeneous-race-free memory models

Hower

Hechtman

Beckmann

et al. 2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

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Commodity heterogeneous systems (e.g., integrated CPUs and GPUs), now support a unified, shared memory address space for all components. Because the latency of global communication in a heterogeneous system can be prohibitively high, heterogeneous systems (unlike homogeneous CPU systems) provide synchronization mechanisms that only guarantee ordering among a subset of threads, which we call a scope. Unfortunately, the consequences and semantics of these scoped operations are not yet well understood. Without a formal and approachable model to reason about the behavior of these operations, we risk an array of portability and performance issues.In this paper, we embrace scoped synchronization with a new class of memory consistency models that add scoped synchronization to data-race-free models like those of C++ and Java. Called sequential consistency for heterogeneousrace-free (SC for HRF), the new models guarantee SC for programs with "sufficient" synchronization (no data races) of "sufficient" scope. We discuss two such models. The first, HRF-direct, works well for programs with highly regular parallelism. The second, HRF-indirect, builds on HRFdirect by allowing synchronization using different scopes in some cases involving transitive communication. We quantitatively show that HRF-indirect encourages forward-looking programs with irregular parallelism by showing up to a 10% performance increase in a task runtime for GPUs.

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Section: Memory Consistency Modelsmentioning

confidence: 99%

Heterogeneous-race-free memory models

Hower

Hechtman

Beckmann

et al. 2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

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“…Sequent Balance (1986) -intelligent interrupt bus [52]. The SLIC bus interrupts the processor currently running the program with least priority.…”

Section: Synchronization By Symmetric Interruptmentioning

confidence: 99%

A sequencing-based taxonomy of I/0 systems and review of historical machines

Smotherman

1989

SIGARCH Comput. Archit. News

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A new taxonomy for I/O systems is proposed that is based on the program sequencing necessary for the control of I/O devices. A review of historical machines demonstrates the need for a more comprehensive categorization than previously published and reveals the historical firsts of I/O interrupts in the NBS DYSEAC, DMA in the IBM SAGE (AN/FSQ-7), the interrupt vector concept in the Lincoln Labs TX-2, and fully symmetric I/O in the Burroughs D-825 multiprocessor.

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“…A large number of cache memory models for multiprocessor systems have been suggested. Write-through models provide the best balance of performance and economy [7]. Copy-back models are the more complex of the two alternatives, but provide a performance increase during read transactions and, moreover, during write transactions …”

Section: Introductionmentioning

confidence: 99%

A process cache memory for tightly coupled multiprocessor systems

Prete

1992

Proceedings of the 30th Annual Southeast Regional Conference on - ACM-SE 30

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C o s i m o A n t o n i o Prete D i p a r t i m e n t o di I n g e g n e r i a d e l l~n f o n u a z i o n e , Universit~ di Pisa, V i a Diotisalvi, 2 -5 6 1 2 6 Pisa (Italy) prete @ iet.unipi.it A b s t r a c tAnalysis of the simulation outputs and of the behaviour of some prototypes of shared-bus multiprocessors with cache memories showed that: (i) system performance depends on the percentage of write operations operating on shared copies and (ii) some events (such as process migration, execution of input~output interrupt routines on different processors, and so on) create a high number of shared copies derived from memory blocks belonging to private data of processes. Starting from these results, we have designed a new coherence protocol which works to reduce the number of shared copies. The basic new idea lies in (i) identifying the copies unused by the running process and (ii) destroying them when they are involved in shared-bus transactions. This paper describes this idea, the coherence protocol, the cache architecture requirements needed to realize such an idea.

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The Balance multiprocessor system

Cited by 35 publications

References 5 publications

Heterogeneous-race-free memory models

Heterogeneous-race-free memory models

A sequencing-based taxonomy of I/0 systems and review of historical machines

A process cache memory for tightly coupled multiprocessor systems

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