A process cache memory for tightly coupled multiprocessor systems

Abstract

C o s i m o A n t o n i o Prete D i p a r t i m e n t o di I n g e g n e r i a d e l l~n f o n u a z i o n e , Universit~ di Pisa, V i a Diotisalvi, 2 -5 6 1 2 6 Pisa (Italy) prete @ iet.unipi.it A b s t r a c tAnalysis of the simulation outputs and of the behaviour of some prototypes of shared-bus multiprocessors with cache memories showed that: (i) system performance depends on the percentage of write operations operating on shared copies and (ii) some events (such as process migration, execution of input~output interrupt routines on different processors, and so on) create a high number of shared copies derived from memory blocks belonging to private data of processes. Starting from these results, we have designed a new coherence protocol which works to reduce the number of shared copies. The basic new idea lies in (i) identifying the copies unused by the running process and (ii) destroying them when they are involved in shared-bus transactions. This paper describes this idea, the coherence protocol, the cache architecture requirements needed to realize such an idea.