A trace-driven simulator for performance evaluation of cache-based multiprocessor systems

Abstract

We describe a simulator which emulates the activity of a shared memory, common bus multiprocessor system with private caches. Both kernel and user program activities are considered, thus allowing an accurate analysis and evaluation of coherence protocol performance. The simulator can generate synthetic traces, based on a wide set of input parameters which specify processor, kernel and workload features. Other parameters allow us to detail the multiprocessor architecture for which the analysis has to be carried out. An actual-trace-driven simulation is possible, too, in order to evaluate the performance of a specific multiprocessor with respect to a given workload, if traces concerning this workload are available. In a separate section, we describe how actual traces can also be used to extract a set of input parameters for synthetic trace generation. Finally, we show how the simulator may be successfully employed to carry out a detailed performance analysis of a specific coherence protocol.Index Terms-Cache memory, multiple cache consistency, coherence protocol, multiprocessor, performance analysis, tracedriven simulation.[29] Q. Yang, L.N. Bhuyan, and B.C. Liu, "Analysis and comparison of cache coherence protocols for a packet-switched multiprocessor," IEEE Cosimo Antonio Prete received his degree in electronic engineenng, cum laude, in 1982 and his PhD from the University of Pisa in 1989 He is currently an associate professor of computer engineenng at the Department of Electncal, Computer, and Telecommunication Engineenng of the University of Pisa, Italy He has performed research in debugging for real-time software development for Alenia in Rome, Italy, and multiprocessor architecture for Olivetti in Ivrea, Italy He has also conducted research in debugging environments' distnbuted systems, in commit protocols for distnbuted transactions, in coherence protocols for tightly coupled multiprocessor systems, and in software environments for the teaching of computer architecture He is project manager for the University of Pisa of 1) the Espnt Tracs project (Flexible Real-Time Environment for Traffic Control Systems, supported by the European Communities), and 2) the Cache-Sim project (a framework for the modeling and simulation of cache memones in ARM systems, supported by VLSI Technology Inc , San Jose, Cahf ) Now his research interests include cache memones, multiprocessor organizabon, and programming environments for parallel and distnbuted systems Dr Prete is a member of the IEEE Computer Society Gianpaolo Prina received his degree in electronic engineering, cum laude, from the University of Pisa in 1992. Now he is a PhD student in computer engineering at the Scuola Superiore di Studi Universitari e di Perfezionamento S. Anna in Pisa, Italy He is involved at the Department of Electncal, Computer, and Telecommunication Engineering of the University of Pisa in the Cache-Sim project (a framework for the modeling and simulation of cache memones in ARM systems, supported by VLSl Technology Inc., San Jose, Calif) His re...

Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload

“…Trace Factory then models the execution of complex multiprogrammed workloads by combining multiple source traces and simulating system calls (which could also involve I/O activity), process scheduling and virtual-to-physical address translation. Finally, Trace Factory produces the references (target trace, Table 2) furnished as input to a memory-hierarchy simulator [31]. Trace Factory generates references according to an on-demand policy: it produces a new reference when simulator requests one, so that the timing behavior imposed by the memory subsystem conditions the reference production [17,18].…”

“…The methodology that we used is based on trace-driven simulation [19,31,36,47] and on the simulation of the three kernel activities that most affect performance: system calls, process scheduling, and virtual-to-physical address translation.…”

“…We believe that this metric provides a better measurement than execution time, since: (i) we are focusing on the memory performance rather than on the processorcore performance, and (ii) we do not execute a single program, in our simulations, but a combination of portions of programs. In these conditions, the machine is fully stressed, and GSP gives the necessary comparability when the performance evaluation requires varying the number of processors and other system parameters [2,16,31], while assuming a fixed internal processor architecture.…”

“…As done in past works [2,16,18,28,31] rather than using the execution time to compare the performance of a multiprocessor system, we measured the global performance by using a single figure, which expresses the computational power delivered by the machine: the global system power (GSP). The GSP represents the number of processors of an ideal machine that does not have delay in accessing memory:…”

Process Migration Effects on Memory Performance of Multiprocessor Web-Servers

“…The simulation methodology relies on trace-driven technique, by means of Trace Factory environment [8], [15].…”