The asynchronous 24MB on-chip level-3 cache for a dual-core Itanium-family processor

Wuu, John; Weiss, D.; Morganti, C.; Dreesen, M.

doi:10.1109/isscc.2005.1494082

Cited by 26 publications

(11 citation statements)

References 5 publications

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“…Hence, the granularity of ECC can be much larger, reducing ECC overhead. The Intel Itanium processor, for example, uses a 10-bit SEC-DED code that protects 256 bits of data [35] with an ECC overhead of only 5%. Other processors, however, use smaller ECC granularity even with L1 write-back caches to provide higher error correction capabilities.…”

Section: Information Redundancymentioning

confidence: 99%

Flexible cache error protection using an ECC FIFO

Yoon

Erez

2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

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We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of adding redundant ECC information to each cache line, our ECC FIFO mechanism off-loads the extra information to off-chip DRAM. We augment each cache line with a tier-1 code, which provides error detection consuming limited resources. The redundancy required for strong protection is provided by a tier-2 code placed in off-chip memory. Because errors that require tier-2 correction are rare, the overhead of accessing DRAM is unimportant. We show how this method can save 15 − 25% and 10 − 17% of on-chip cache area and power respectively while minimally impacting performance, which decreases by 1% on average across a range of scientific and consumer benchmarks.

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Section: Information Redundancymentioning

confidence: 99%

Flexible cache error protection using an ECC FIFO

Yoon

Erez

2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

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“…The difference is that Montecito allocates the 32 queue entries more efficiently, which provides a higher concurrency level than with the Itanium 2. low latency; there is no clock, only a read or write valid indication. 5 The read signal is coincident with index and way values that initiate L3 data-array accesses. Four cycles later, the entire 128-byte line is available and latched.…”

Section: Cache Hierarchymentioning

confidence: 99%

Montecito: A Dual-Core, Dual-Thread Itanium Processor

2005

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“…To minimize process variation effects (and clock-related power consumption), the L3 cache has a selftimed asynchronous design style. 9 Asynchronous design is challenging because few design automation tools exist for it, and validating the design is difficult. This challenge is manageable in the case of the Itanium 2, which is a relatively simple in-order design.…”

Section: Microarchitectural Techniquesmentioning

confidence: 99%