Impact of Parameter Variations on Circuits and Microarchitecture

Unsal, Osman S.; Tschanz, Jim; Bowman, Keith; De, Vivek; Vera, Xavier; González, Antonio; Ergin, Oğuz

doi:10.1109/mm.2006.122

Cited by 94 publications

(42 citation statements)

References 23 publications

(26 reference statements)

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“…We suspect that the affected memory cells are in physical proximity or alignment (row, column, bank) however the memory controller maps them to different address words. These observations suggest that the root cause of such simultaneous errors could be linked to local hardware defects due to manufacturing variability [14], but they could also be related to external factors that affect multiple regions of the devices at the same time.…”

Section: Multiple Simultaneous Corruptionsmentioning

confidence: 99%

Unprotected Computing: A Large-Scale Study of DRAM Raw Error Rate on a Supercomputer

Bautista-Gomez

Zyulkyarov

Unsal

et al. 2016

SC16: International Conference for High Performance Computing, Networking, Storage and Analysis

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Abstract-Supercomputers offer new opportunities for scientific computing as they grow in size. However, their growth also poses new challenges. Resilience has been recognized as one of the most pressing issues to solve for extreme scale computing. Transistor scaling in the single-digit nanometer era and power constraints might dramatically increase the failure rate of next generation machines. DRAM errors have been analyzed in the past for different supercomputers but those studies are usually based on job scheduler logs and counters produced by hardwarelevel error correcting codes. Consequently, little is known about errors escaping hardware checks, which lead to silent data corruption. This work attempts to fill that gap by analyzing memory errors for over a year on a cluster with about 1000 nodes featuring low-power memory without error correction. The study gathered millions of events recording detailed information of thousands of memory errors, many of them corrupting multiple bits. Several factors are analyzed, such as temporal and spatial correlation between errors, but also the influence of temperature and even the position of the sun in the sky. The study showed that most multi-bit errors corrupted non-adjacent bits in the memory word and that most errors flipped memory bits from 1 to 0. In addition, we observed thousands of cases of multiple single-bit errors occurring simultaneously in different regions of the memory. These new observations would not be possible by simply analyzing error correction counters on classical systems. We propose several directions in which the findings of this study can help the design of more reliable systems in the future.

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Section: Multiple Simultaneous Corruptionsmentioning

confidence: 99%

Unprotected Computing: A Large-Scale Study of DRAM Raw Error Rate on a Supercomputer

Bautista-Gomez

Zyulkyarov

Unsal

et al. 2016

SC16: International Conference for High Performance Computing, Networking, Storage and Analysis

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“…Several techniques have been proposed to minimize process variation at the circuit and microarchitectural levels at different costs [Unsal et al 2006;Tschanz et al 2002]. There has been extensive research in the area of task allocation and scheduling for MPSoC [Braun et al 2001;Stuijk et al 2007;Bonfietti et al 2009Bonfietti et al , 2010Wang et al 2007;Chon and Kim 2009;Singhal and Bozorgzadeh 2008;Huang and Xu 2010].…”

Section: Related Workmentioning

confidence: 99%

“…However, scaling the minimum feature sizes in deep-submicron technologies has also brought variations in key transistor parameters, such as channel length and device and interconnect width. This phenomenon, known as process variation [Unsal et al 2006], significantly impacts the maximum supported frequency of individual cores in an MPSoC [Bowman et al 2002;Eisele et al 1997]. It is shown [Miranda et al 2009] that the variation in the longest path delay (the inverse of FMAX) of a very long instruction word (VLIW) processor, manufactured at 32nm technology, is up to 40%.…”

Section: Introductionmentioning

confidence: 99%

Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs

Mirzoyan

Åkesson

Goossens

2014

ACM Trans. Embed. Comput. Syst.

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As technology scales, the impact of process variation on the maximum supported frequency (FMAX) of individual cores in a multiprocessor system-on-chip (MPSoC) becomes more pronounced. Task allocation without variation-aware performance analysis can greatly compromise performance and lead to a significant loss in yield, defined as the percentage of manufactured chips satisfying the application timing requirement. We propose variation-aware task allocation for best-effort and real-time streaming applications modeled as task graphs. Our solutions are primarily based on the throughput requirement, which is the most important timing requirement in many real-time streaming applications.The four main contributions of this work are (1) distinguishing best-effort firm real-time and soft real-time application classes, which require different optimization criteria, (2) using dataflow graphs, which are well suited for modeling and analysis of streaming applications, we explicitly model task execution both in terms of clock cycles (which is independent of variation) and seconds (which does depend on the variation of the resource), which we connect by an explicit binding, (3) we present two optimization approaches, which give different improvement results at different costs, (4) we present both exhaustive and heuristic algorithms that implement the optimization approaches. Our variation-aware mapping algorithms are tested on models of seven real applications and are compared to mapping methods that are unaware of hardware variation. Our results demonstrate (1) improvements in the average performance (3% on average) for best-effort applications, and (2) for firm real-time and soft real-time applications, yield improvements of up to 27% with an average of 15%, showing the effectiveness of our approaches.

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“…It is also rather unclear how scalable the mixed digital/analog designs would be in the face of increasing process variations as we move up to higher values of n and deeper into submicrometer regimes [14].…”

Section: Review Of Previous Workmentioning

confidence: 99%

Efficient Hamming Weight Comparators for Binary Vectors Based on Accumulative and Up/Down Parallel Counters

Parhami

2009

IEEE Trans. Circuits Syst. II

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Abstract-New counting-based methods for comparing the Hamming weight of a binary vector with a constant, as well as comparing the Hamming weights of two input vectors, are proposed. It is shown that the proposed comparators are faster and simpler, both in asymptotic sense and for moderate vector lengths, compared with the best available fully digital designs. These speed and cost advantages result from a more efficient population counting, as well as the merger of counting and comparison operations, via accumulative and up/down parallel counters.

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Impact of Parameter Variations on Circuits and Microarchitecture

Cited by 94 publications

References 23 publications

Unprotected Computing: A Large-Scale Study of DRAM Raw Error Rate on a Supercomputer

Unprotected Computing: A Large-Scale Study of DRAM Raw Error Rate on a Supercomputer

Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs

Efficient Hamming Weight Comparators for Binary Vectors Based on Accumulative and Up/Down Parallel Counters

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