Efficient Hamming Weight Comparators for Binary Vectors Based on Accumulative and Up/Down Parallel Counters

Parhami, Behrooz

doi:10.1109/tcsii.2008.2010176

Cited by 50 publications

(28 citation statements)

References 20 publications

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“…Finally, the third stage is where the stochastic output is converted back to a binary output by counting the number of ones. A combinational circuit is implemented for the conversion of stochastic to binary number by counting the number of ones in the SN by making use of the Hamming weight counter principle [28]. …”

Section: Parallel Implementation Of Proposed Sngs For Scmentioning

confidence: 99%

Implementation Of Reconfigurability Number Generators For Digital Bit Stream Signals

2018

IJRTER

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The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bit stream processing and excessive runtime requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs) and parallel stochastic bit stream processing, which are well suited to leverage FPGA's reconfigurability and abundant internal memory resources. the proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively.

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Section: Parallel Implementation Of Proposed Sngs For Scmentioning

confidence: 99%

Implementation Of Reconfigurability Number Generators For Digital Bit Stream Signals

2018

IJRTER

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“…In this paper, an STB conversion unit is used that converts the parallel stochastic output into a binary number by using simple adder circuits. this circuit can count the number of ones in a parallel bit stream by using the Hamming weight counter principle [28]. the structure of the STB conversion unit for counting the number of ones in eight parallel stochastic bits of a 256-bit stream length consists of four half adders, two two-bit adders, a three-bit adder, an eight-bit register and a four-bit adder.…”

Section: Third Stagementioning

confidence: 99%

Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing

Seva

Metku

Choi

2017

JLPEA

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Abstract:The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs) and parallel stochastic bitstream processing, which are well suited to leverage FPGA's reconfigurability and abundant internal memory resources. the proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively.

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“…(21), our design covers comparisons, Hamming distance measurements, and filtering of pre-selected Hamming weights. Most previously proposed Hamming-related module designs [9,10,13,16,17], by contrast, are aimed at measuring distances between, or comparing, bit-vectors, entailing only one comparison instead of two parallel ones. Additionally, the aforementioned functionalities of our design are applicable to N-bit input XH, with YHL and YHU potentially being of same width or narrower.…”

Section: Speed and Cost Comparisonmentioning

confidence: 99%

“…However, the resulting circuit still suffers from many of the same design problems, with the further drawback of limited and narrow applications. Parhami [9] has proposed a more general Hamming-weight comparator using the notion of signed bits. His design, though improving on earlier proposal, still entails large gate count, delay, and power.…”

Section: Speed and Cost Comparisonmentioning

confidence: 99%

“…Many circuits in the latter class have been designed to cater to specific applications or application domains involving Hamming vectors and weights. Among the many available options, one finds all-digital designs [9][10][11][12], digital designs based on the technology-ratioed approach [13][14][15], designs using lookup tables and approximations [16][17][18], and, in the case of our prior contributions, mixed digital-analog designs that are more compact and use highspeed parallel evaluation [19,20]. A general view, covering both radix-based weights and unit weights, is the assignment of arbitrary ''importance'' to various features [21].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A mixed analog–digital fast hamming-weight filtering circuit using switched-capacitor arrays

Abdel-Hafeez

Parhami

Alhammouri

2015

Analog Integr Circ Sig Process

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Many circuit design applications rely on an intermediate sequence to carry a decision to the next circuit stage. The decision may be carried by a weighted pattern of N bits, with the weights being selected in a way that optimizes the circuit implementation or some aspect of performance. For example, when the weights are consecutive powers of 2 beginning with 1 = 2 0 , we have the standard binary representation. As another example, when all the weights are 1, we have the unary representation that encodes a value k by k asserted bits and N-k unasserted bits (a weightk bit vector of length N). In this paper, we present the design of a circuit that screens a unary representation to verify that the represented value falls between preset lower and upper limits l and u, passing through any string that represents a value in the interval [l, u] and outputting the all-0 s bit pattern otherwise. Our mixed analog-digital circuit implementation, based on switched-capacitor arrays, provides a decision output within a clock cycle of 4 ns for 16-bit unary representation, when realized with 0.15 lm TSMC technology. The latter results were obtained with normal, per-bit capacitance of 200 fF and single-clock-cycle operation. As an added benefit, our filtering circuit can form the basis for designing a cost-effective Hamming decoder circuit.

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Efficient Hamming Weight Comparators for Binary Vectors Based on Accumulative and Up/Down Parallel Counters

Cited by 50 publications

References 20 publications

Implementation Of Reconfigurability Number Generators For Digital Bit Stream Signals

Implementation Of Reconfigurability Number Generators For Digital Bit Stream Signals

Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing

A mixed analog–digital fast hamming-weight filtering circuit using switched-capacitor arrays

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