Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing

Abstract

Abstract:The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs) and parallel stochastic bitstream processing, which are well suited to leverage FPGA's reconfigurability and abundant internal memory resources. the proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively.

Energy-Performance Scalability Analysis of a Novel Quasi-Stochastic Computing Approach

“…The operation of these circuits rely on the type of number interpretations, namely unipolar (UP), bipolar (BP) or inverted bipolar (IBP) formats as presented in [19]. The unipolar format represents the real number x in the range of [0, 1], using bipolar x is represented in between [−1, 1] and IBP ranges from [−1, 1], where the Boolean values 0 and 1 are represented as 1 and −1 in the stochastic number (SN) [11]. Detailed explanations of various SN formats are clearly discussed in [14].…”

“…The probability value in SC is represented by a binary bitstream of 0s and 1s with specific length L [19]. For the binary representation of 0.5, in the bitstream of length L, half of the bits are represented by 1s and the other half with 0s [11]. For example, one way of representing 0.5 with a bitstream of 8 bits is 01010101.…”

“…However, mainstream adoption of SC is limited due to the long run-time and inaccuracy [1]. As explained in [11], a random number generator (RNG), also known as a stochastic number generator (SNG), plays a significant role in determining the area and energy consumption. The commonly used SNG is the linear feedback shift register (LFSR), and several optimization techniques to improve the output accuracy of the LFSR-based SNGs are presented in the literature [12][13][14][15][16][17][18].…”

“…To address this issue, [11] introduced a quasi-stochastic bit sequence generation (QSNG) that utilizes the distributed memory elements of a field-programmable gate array (FPGA) for designing the SNGs. However, no comment on energy reduction has been reported in [11]. Therefore, in this work a detailed analysis and methodology for energy reduction is presented to improve the overall performance.…”

Novel Stochastic Computing for Energy-Efficient Image Processors

“…Stochastic computing-which is an approximate computation method based on probabilities-was introduced in the 1960s [3]. Because of its tolerance toward errors and the use of very simple circuits, stochastic computing is particularly used in applications such as image processing and digital filters [4][5][6][7][8][9][10][11][12][13][14][15][16]. Also, it is possible to merge various inputs and reduce the dimension of the stochastic computing [17].…”