The architecture of the LR33000: a MIPS compatible RISC processor for embedded control applications

Caulk, B.; Desai, Soham Jayesh; Gavrielov, M.; Harper, G.; Jones, D. H.; Kwong, Man Kam; Murzello, M.; Oke, T.; Patel, Jaymin; Peck, R.A.; Jiang, Wei; Yang, Ran

doi:10.1109/iccd.1991.139911

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

DOI: 10.1109/iccd.1991.139911

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The architecture of the LR33000: a MIPS compatible RISC processor for embedded control applications

B. Caulk¹,

Soham Jayesh Desai²,

M. Gavrielov³

et al.

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Cited by 2 publications

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A Tightly Coupled Pipelined Graphics Coprocessor Integrated With A RISC CPU

Desai¹,

Caulk²

Proceedings of the IEEE Custom Integrated Circuits Conference

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This paper describes lhe architecture and implementation of a graphics coprocessor integrated with a MIPS-1 (R3000) compatible CPU core. The design of the graphics coprocessor has been oprimiscd for accelerating low level graphics operations typical in X Windows applications. I t has been implemented us coprocessor 2 using the coprocessor interface available on the CPU core. A set of specifically designed coprocessor 2 graphics instructions execute on the coprocessor and process pixel data fetched by dedicated DMA channels through a high bandwidth memory interface. The combination of the graphics coprocessor und high Oundwidlh memory interface result in a very high perfnrmcince.

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A Tightly Coupled Pipelined Graphics Coprocessor Integrated With A RISC CPU

Desai¹,

Caulk²

Proceedings of the IEEE Custom Integrated Circuits Conference

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The architecture of the LR33020 graphX processor: a MIPS-RISC based X-terminal controller

Desai¹

Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers &Amp; Processors

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The architecture of the LR33000: a MIPS compatible RISC processor for embedded control applications

Cited by 2 publications

References 2 publications

A Tightly Coupled Pipelined Graphics Coprocessor Integrated With A RISC CPU

A Tightly Coupled Pipelined Graphics Coprocessor Integrated With A RISC CPU

The architecture of the LR33020 graphX processor: a MIPS-RISC based X-terminal controller

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