The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer

Iwata, Atsushi; Sakimura, N.; Nagata, Makoto; Matsukawa, Takashi

doi:10.1109/82.775391

Cited by 93 publications

(48 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…13 shows the microphotograph and layout of the ADC fabricated in ST 45 nm CMOS. It has a core area of 0.004 mm 2 and a total area of 0.096 mm 2 including calibration. The ADC full-scale input is 0.6 Vpp with a common-mode volt-age of 0.7 V. With 1 V supply, the power consumption is 7.8 mW operating at 5 GS/s (27% in clock buffers, 58% in VTCs and time comparators, and 15 % in the output buffers, latches, decoder and calibration DAC).…”

Section: Vtc Nonlinearitymentioning

confidence: 99%

“…Thus, both the speed and the energy efficiency are greatly limited by the number of bit counters that also expand rapidly with the bit resolution. While time-domain converters have been widely adopted in sigma delta ADCs for their 1st order noise shaping characteristic [2], [3], in multi-bit SAR ADC for replacing multiple comparators [4] or in the digital slope SAR-assisted ADC, the required long counting period [5] limits their operation in GHz applications. Thanks to technology scaling, both flash and time-based architectures experienced significant advancements on both speed and energy efficiency Due to the small device size and less logic gate delay.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 2.6-mW 4-b 4.8-GS/s Dual-Edges-Triggered Time-Based Flash ADC

Vaidya¹

2017

IJRASET

View full text Add to dashboard Cite

Abstract-This paper proposes a 4-b 5-GS/s time-based flash ADC in 45-nm digital CMOS technology, which utilizes both rising and falling edges of the clock for sampling and quantiza-tion. A dual-edge-triggered scheme reduces the dynamic power consumption of a voltage-to-time converter and the clock buffers by half. We doubled both the reset and the available regeneration times by interleaving the time comparators. The ADC has a low input capacitance and the calibration circuit is included on-chip for suppressing various mismatches. The prototype running at 5 GS/s consumes 2.6 mW from a 0.8-V supply and achieves a signal-to-noise and distortion ratio of 26.19 dB at Nyquist. Index Terms-Analog-to-digital converter (ADC), flash, time-based dual-edge-triggered. I.INTRODUCTION The required bandwidth of communication systems has grown rapidly, and applications such as the serial links need GS/s ADCs with great power efficiency and small area. Flash ADC is known as the fastest single channel ADC architecture which relies on the parallel operation of comparators. However for higher resolution, the number of comparators increase exponentially, which not only leads to a large area occupation but also significant amount of power consumption [1]. Another type of ADC architecture relying on massively parallel operation is the time-based ADC which mainly consists of time-to-digital converters (TDCs). The simplest form of a TDC is a digital counter. Thus, both the speed and the energy efficiency are greatly limited by the number of bit counters that also expand rapidly with the bit resolution. While time-domain converters have been widely adopted in sigma delta ADCs for their 1st order noise shaping characteristic [2], [3], in multi-bit SAR ADC for replacing multiple comparators [4] or in the digital slope SAR-assisted ADC, the required long counting period [5] limits their operation in GHz applications. Thanks to technology scaling, both flash and time-based architectures experienced significant advancements on both speed and energy efficiency

show abstract

Section: Vtc Nonlinearitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 2.6-mW 4-b 4.8-GS/s Dual-Edges-Triggered Time-Based Flash ADC

Vaidya¹

2017

IJRASET

View full text Add to dashboard Cite

show abstract

“…A circuit to extract phase was proposed in [5] assuming the rectangle waveform of the VCO output, but it is not suitable for high frequency operation. Another method is embedding the FMDSM into the inner part of the 2nd order DSM [3]. However, this has a global feedback loop for the outer DSM and the overall operation frequency should be restricted by it.…”

Section: Fmdsmmentioning

confidence: 99%

“…However, its use is restricted to relatively low frequency applications due to the limitation of the sampling frequency. The DSM using frequency modulated intermediate signal (FMDSM) [2,3,4] has significant advantages that it has no feedback digital-analog converter (DAC) restricting the operation frequency, and hence, is suitable for high frequency operation. However, the FMDSM has been not widely used so far, since it is difficult to apply the FMDSM concept to higher order DSMs.…”

Section: Introductionmentioning

confidence: 99%

Dual-clock MASH delta-sigma modulator employing a frequency modulated intermediate signal

Maezawa

Sakou

Matsubara

et al. 2006

IEICE Electron. Express

View full text Add to dashboard Cite

A dual-clock MASH (multi-stage noise shaping) deltasigma modulator (DSM) is proposed for high performance analog-digital converter. This employs a DSM using a frequency modulated intermediate signal (FMDSM) for the last stage. The sampling clock frequency for the last stage can be increased due to the features of the FMDSM. It is shown that this can increase the SNR beyond the conventional MASH DSMs.

show abstract

“…However, even harmonics still remain. Iwata et al [5] and Straayer and Perrott [6] employed analog feedback using a digital-to-analog converter (DAC), which needs many complex analog components.…”

Section: Introductionmentioning

confidence: 99%

A Multi-bit VCO-based Linear Quantizer with Frequency-to-current Feedback using a Switched-capacitor Structure

Park¹,

Ryu²,

Sung³

et al. 2015

IEIE Transactions on Smart Processing and Computing

View full text Add to dashboard Cite

Abstract:In this letter, we present a new linearization method for a voltage controlled oscillator (VCO)-based quantizer in an analog-to-digital converter (ADC). The nonlinearity of the VCO generates unwanted harmonic spurs and reduces the signal-to-noise and distortion ratio (SNDR) of the VCO-based quantizer. This letter suggests a frequency-to-current feedback method to effectively suppress harmonic distortion. The proposed method decreases the harmonic spurs by more than 53 dB. And a VCO-based quantizer employing the proposed linearization method achieves a high SNDR of 74.1 dB.

show abstract

The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer

Cited by 93 publications

References 3 publications

A 2.6-mW 4-b 4.8-GS/s Dual-Edges-Triggered Time-Based Flash ADC

A 2.6-mW 4-b 4.8-GS/s Dual-Edges-Triggered Time-Based Flash ADC

Dual-clock MASH delta-sigma modulator employing a frequency modulated intermediate signal

A Multi-bit VCO-based Linear Quantizer with Frequency-to-current Feedback using a Switched-capacitor Structure

Contact Info

Product

Resources

About