A 2.6-mW 4-b 4.8-GS/s Dual-Edges-Triggered Time-Based Flash ADC

Abstract

Abstract-This paper proposes a 4-b 5-GS/s time-based flash ADC in 45-nm digital CMOS technology, which utilizes both rising and falling edges of the clock for sampling and quantiza-tion. A dual-edge-triggered scheme reduces the dynamic power consumption of a voltage-to-time converter and the clock buffers by half. We doubled both the reset and the available regeneration times by interleaving the time comparators. The ADC has a low input capacitance and the calibration circuit is included on-chip for suppressing various mismatches. The prototype running at 5 GS/s consumes 2.6 mW from a 0.8-V supply and achieves a signal-to-noise and distortion ratio of 26.19 dB at Nyquist. Index Terms-Analog-to-digital converter (ADC), flash, time-based dual-edge-triggered. I.INTRODUCTION The required bandwidth of communication systems has grown rapidly, and applications such as the serial links need GS/s ADCs with great power efficiency and small area. Flash ADC is known as the fastest single channel ADC architecture which relies on the parallel operation of comparators. However for higher resolution, the number of comparators increase exponentially, which not only leads to a large area occupation but also significant amount of power consumption [1]. Another type of ADC architecture relying on massively parallel operation is the time-based ADC which mainly consists of time-to-digital converters (TDCs). The simplest form of a TDC is a digital counter. Thus, both the speed and the energy efficiency are greatly limited by the number of bit counters that also expand rapidly with the bit resolution. While time-domain converters have been widely adopted in sigma delta ADCs for their 1st order noise shaping characteristic [2], [3], in multi-bit SAR ADC for replacing multiple comparators [4] or in the digital slope SAR-assisted ADC, the required long counting period [5] limits their operation in GHz applications. Thanks to technology scaling, both flash and time-based architectures experienced significant advancements on both speed and energy efficiency