The Applications of NVM Technology in Hardware Security

Yang, Chaofei; Liu, Beiye; Wang, Yandan; Chen, Yiran; Hai, Li; Zhang, Xian; Sun, Guangyu

doi:10.1145/2902961.2903043

Cited by 8 publications

(3 citation statements)

References 23 publications

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“…Memristors are differed from each other and classified according to the technology of creation, materials and related features. In this paper we propose a design of TRNG circuit that is based on Phase-Change Memory device (Ge 2 Sb 2 T e 2 ), which is known as GST memristor [4], [5], [6], [7]. For the present time there is no existing GST memristor model, that is why its characteristical equations and parameters should be investigated in order to create its emulator circuit.…”

Section: Introductionmentioning

confidence: 99%

Notice of Retraction: Implementation of True Random Number Generator based on Double-Scroll Attractor circuit with GST memristor emulator

Abzhanova

Dolzhikova

James

2018

2018 International Conference on Computing and Network Communications (CoCoNet)

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The cryptographic security provided by various techniques of random number generator (RNG) construction is one of the developing researches areas today. Among various types of RNG, the true random bit generator (TRBG) can be considered as the most unpredictable and most secured because its randomness seed is generated from chaotic sources. This paper proposes a design of TRBG model based on double-scroll attractors circuits with GST memristor. After implementation and simulation of the chaotic circuit with GST memristor emulator, the chaotic behavior of the output voltage and inductor current were received. Moreover, their dependence on the input voltage revealed the close to double-scroll form. The randomness generated from the proposed circuit was tested by receiving Fast Fourier Transform (FFT) and Lyapunov exponents of the output voltage.

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Section: Introductionmentioning

confidence: 99%

Notice of Retraction: Implementation of True Random Number Generator based on Double-Scroll Attractor circuit with GST memristor emulator

Abzhanova

Dolzhikova

James

2018

2018 International Conference on Computing and Network Communications (CoCoNet)

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“…The Gaussian distribution observed in this paper was also mentioned in the recent experiment of the HfO 2 -based memristor array [ 29 ]. The Gaussian distribution function can also be found in the threshold voltage of flash memory cells programmed by the program-verify scheme such as ISPP [ 44 , 45 ].…”

Section: Discussionmentioning

confidence: 99%

Asymmetrical Training Scheme of Binary-Memristor-Crossbar-Based Neural Networks for Energy-Efficient Edge-Computing Nanoscale Systems

2019

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For realizing neural networks with binary memristor crossbars, memristors should be programmed by high-resistance state (HRS) and low-resistance state (LRS), according to the training algorithms like backpropagation. Unfortunately, it takes a very long time and consumes a large amount of power in training the memristor crossbar, because the program-verify scheme of memristor-programming is based on the incremental programming pulses, where many programming and verifying pulses are repeated until the target conductance. Thus, this reduces the programming time and power is very essential for energy-efficient and fast training of memristor networks. In this paper, we compared four different programming schemes, which are F-F, C-F, F-C, and C-C, respectively. C-C means both HRS and LRS are coarse-programmed. C-F has the coarse-programmed HRS and fine LRS, respectively. F-C is vice versa of C-F. In F-F, both HRS and LRS are fine-programmed. Comparing the error-energy products among the four schemes, C-F shows the minimum error with the minimum energy consumption. The asymmetrical coarse HRS and fine LRS can reduce the time and energy during the crossbar training significantly, because only LRS is fine-programmed. Moreover, the asymmetrical C-F can maintain the network’s error as small as F-F, which is due to the coarse-programmed HRS that slightly degrades the error.

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“…The demand for logic nonvolatile memories (NVMs), which are fully compatible with advanced CMOS logic processes, is growing fast in the Internet of Things (IOT) era. [1][2][3][4][5][6][7][8][9][10][11] Full compatibility with standard processes of logic NVMs can greatly reduce developmental costs and can be adapted to different generations of technology nodes. Compact cell arrays, high programming and accessing speed, and low power consumption are also desirable features.…”

Section: Introductionmentioning

confidence: 99%

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

Wang¹,

Chien²,

Hsu³

et al. 2018

Jpn. J. Appl. Phys.

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In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

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The Applications of NVM Technology in Hardware Security

Cited by 8 publications

References 23 publications

Notice of Retraction: Implementation of True Random Number Generator based on Double-Scroll Attractor circuit with GST memristor emulator

Notice of Retraction: Implementation of True Random Number Generator based on Double-Scroll Attractor circuit with GST memristor emulator

Asymmetrical Training Scheme of Binary-Memristor-Crossbar-Based Neural Networks for Energy-Efficient Edge-Computing Nanoscale Systems

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

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