Asymmetrical Training Scheme of Binary-Memristor-Crossbar-Based Neural Networks for Energy-Efficient Edge-Computing Nanoscale Systems

Abstract

For realizing neural networks with binary memristor crossbars, memristors should be programmed by high-resistance state (HRS) and low-resistance state (LRS), according to the training algorithms like backpropagation. Unfortunately, it takes a very long time and consumes a large amount of power in training the memristor crossbar, because the program-verify scheme of memristor-programming is based on the incremental programming pulses, where many programming and verifying pulses are repeated until the target conductance. Thus, this reduces the programming time and power is very essential for energy-efficient and fast training of memristor networks. In this paper, we compared four different programming schemes, which are F-F, C-F, F-C, and C-C, respectively. C-C means both HRS and LRS are coarse-programmed. C-F has the coarse-programmed HRS and fine LRS, respectively. F-C is vice versa of C-F. In F-F, both HRS and LRS are fine-programmed. Comparing the error-energy products among the four schemes, C-F shows the minimum error with the minimum energy consumption. The asymmetrical coarse HRS and fine LRS can reduce the time and energy during the crossbar training significantly, because only LRS is fine-programmed. Moreover, the asymmetrical C-F can maintain the network’s error as small as F-F, which is due to the coarse-programmed HRS that slightly degrades the error.

Exploiting defective RRAM array as synapses of HTM spatial pooler with boost-factor adjustment scheme for defect-tolerant neuromorphic systems

“…The enhanced resolution in the output resulted in the improved accuracy. In addition, assuming that the energy to program the crossbar RRAM array was about 4 mJ at a given the number of the RRAMs in the column, the additional energy of 1,000 times less to run the boost-factor adjustment technique was needed 48,49 . This was because the RRAM and other components, which were key components in the hybrid circuit, can be operated quickly, thereby reducing running time as well as area demanded to implement the algorithms.…”

Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training

“…Figure 5d compares the programming time between 10% and 100% retraining of the memristor-based network. For calculating the programming time, we used the transient behavior of memristor’s conductance dynamically changed according to the number of programming pulses, which was reported in the previous publication [14]. Here, the programming time can be calculated with the ‘m’ times the programming pulse width, as mentioned in Figure 1c.…”

“…Here, the programming time can be calculated with the ‘m’ times the programming pulse width, as mentioned in Figure 1c. The number of pulses ‘m’ for programming the memristor’s conductance until the target weight is obtained from the relationship of memristor’s conductance and the number of pulses [14]. The Verilog-A model can model this relationship and it is used in the simulation in this paper.…”

“…The energy-efficient and fast training of memristor-based neural networks are very important in edge-computing applications [14]. For edge-computing, the data are processed not by the high-performance cloud servers, but the edge-node devices, where various physical-world data are sensed, collected, and interpreted [15].…”

“…For the data type, most of data collected at the edge nodes are unstructured data, like images, voices, anomaly patterns, etc. [14,15]. In order to recognize a vast amount of the unstructured data from the physical world, a cognition algorithm that is inspired by the brain’s architecture and function should be used at the edge devices.…”