The application of test structures for the study of surface effects in LSI circuitry

Schlegel, E. S.; Schnable, G. L.

doi:10.1109/t-ed.1969.16762

Cited by 15 publications

(8 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…CVD films frequently have high Na content (18). Sources of Na in the films discussed here are not known, but are probably numerous since Na-free A1 was not used and MOS fabrication procedures were not followed.…”

Section: Discussionmentioning

confidence: 99%

“…Even though bulk and surface leakage currents are negligibly small, they can have indirect effects related to surface charge inversion (16)(17)(18)(19)21). Using a specially fabricated MOS IC, an inversion-induced leakage after autoclave stress was observed (33).…”

Section: Discussionmentioning

confidence: 99%

“…The bulk and surface electrical properties of CVD passivation over metal are important in understanding Na-gettering (4,15) device leakage as affected by lateral charge spreading (16)(17)(18)(19)(20)(21), metal corrosion (22)(23)(24)(25), and moisture effects (24,25).…”

mentioning

confidence: 99%

See 2 more Smart Citations

Bulk and Surface Conduction in CVD SiO2 and PSG Passivation Layers

Comizzoli¹

1976

J. Electrochem. Soc.

View full text Add to dashboard Cite

Measurements of electrical conduction in the bulk of chemical vapor deposited (CVD) SiO.2 and phosphosilicate glass (PSG) passivation layers typically used for over-me~al IC protection are reported. Moisture uptake increases the bulk conductivity, and the moisture effects depend on phosphorus content. The bulk current thermal activation energy of CVD SiO.~ (0.6 eV) is constant with varying moisture exposure. Before moisture exposure, phosphorus-containing glass has an activation energy of 0.8 eV, and it decreases with moisture exposure. Surface conductivity is also reported as a function of relative humidity. Conductivity values are related to IC leakage currents, and it is suggested that bulk currents in PSG should not contribute to aluminum corrosion in the absence of defects, such as cracks or pinholes.SiO~ and phosphosilicate glass (PSG) are important materials in silicon device passivation (1). Thin layers of PSG (hundreds of angstroms) have been described as useful for Na-gettering under gate metal of MOS devices (2-4). Thin layers must be used to avoid instabilities due to PSG polarization (3, 5-7). For overmetal passivation of IC's, thicker layers (about 104fl,) can be used (since polarization of the PSG is unimportant in this geometry). Generally, over-metal layers are deposited by chemical vapor deposition (CVD) (8-11 ). The phosphorus addition lowers intrinsic stress over aluminum metal and provides Na-gettering capability (12), which is particularly useful in plastic packaged devices. In addition, the passivating glass over metal provides important scratch protection during the device production process (13), and serves as insulating protection against loose conducting particles in hermetic packages (14).The bulk and surface electrical properties of CVD passivation over metal are important in understanding Na-gettering (4, 15) device leakage as affected by lateral charge spreading (16-21), metal corrosion (22-25), and moisture effects (24,25).In this report, measurements of bulk electrical conductivity as a function of water uptake and temperature, and surface conductivity as a function of relative humidity (RH) are reported for CVD SiO2 and CVD PSG. The data are used in estimating electrical and moisture effects typical for IC's. Sample PreparationThe glass layers were deposited on degenerate ntype (0.01 ohm-cm) silicon wafers at 450~ at a growth rate of about 1000 A/min to a total thickness of 1 ~m, using a reactor described by Kern (11,26). Phosphorus concentrations, determined by etch rate analysis, are 0, 4.8, and 8.5 weight per cent (w/o) P in the glass. No postdeposition heat-treatments were applied. * Electrochemical Society Active Member.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Bulk and Surface Conduction in CVD SiO2 and PSG Passivation Layers

Comizzoli¹

1976

J. Electrochem. Soc.

View full text Add to dashboard Cite

show abstract

“…Accordingly, SiO2 primary passivation phenomena will not be treated in detail in this paper. The ambient and temperature during application, or during subsequent fusion or heattreatment of the secondary passivating layer may, however, modify the electrical properties of the Si-SiO2 interface, including the mobile and immobile charge density and the fast surface-state density (75,294,309,274,76,193,361,16). While this is particularly true of high-temperature depositions or heat-treatments (temperatures greater than approximately 800~ it also occurs to some extent during low-temperature deposition processes [performed at 450~ or lower (274) ].…”

Section: Thermally Grown Silicon Dioxidesmentioning

confidence: 99%

Passivation Coatings on Silicon Devices

Schnable

Kern

Comizzoli

1975

J. Electrochem. Soc.

View full text Add to dashboard Cite

Passivation coatings are widely used to improve the performance and reliability of silicon devices of various types, ranging from discrete mesa‐type diodes and transistors to complex planar silicon integrated circuits, and including both hermetic and plastic‐encapsulated devices. This paper reviews the materials and techniques used to apply passivation coatings to completed silicon devices. Principal production techniques used in passivation of silicon devices include thermal oxidation, high‐temperature diffusion, high‐temperature chemical vapor deposition of Si3N4 or Al2O3 , low‐temperature chemical vapor deposition of glasslike SiO2 or phosphosilicate layers (deposited at approximately 400°C), rf sputtering of SiO2 , mechanical deposition of glass frit layers which are subsequently fused, and application of organic polymer films.The effects of passivation layers on silicon device reliability are discussed, and the interrelationships among the silicon device, the passivation layer or layers used and the final encapsulation are indicated. Pertinent references on passivation and on related topics are cited in the text.

show abstract

“…It consists mainly of sheet resistors, contact resistors, MOS capacitors, and gated p-n junctions which are listed in table 1. (5)(6)(7)(8)(11)(12)(13), and 1.5 mm (9), and the sides should be 0.13 mm (3) and 0.46 mm (4); all tolerances should be held to ±0.002 mm. The design objectives of this pattern were two fold.…”

Section: A Test Pattern Used At Nbsmentioning

confidence: 99%

Microelectronic test patterns

Buehler¹

1974

View full text Add to dashboard Cite

The application of test structures for the study of surface effects in LSI circuitry

Cited by 15 publications

References 17 publications

Bulk and Surface Conduction in CVD SiO2 and PSG Passivation Layers

Bulk and Surface Conduction in CVD SiO2 and PSG Passivation Layers

Passivation Coatings on Silicon Devices

Microelectronic test patterns

Contact Info

Product

Resources

About