The application of noisy reward/penalty learning to pyramidal pRAM structures

Guan, Y.; Clarkson, T.G.; Gorse, Denise; Taylor, John G.

doi:10.1109/ijcnn.1992.227099

Cited by 2 publications

(1 citation statement)

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“…Up to 1280 neurons can be interconnected by combining five chips. Learning (Clarkson and Ng 1993, Clarkson et al 1991a, b, 1992b, c, Gorse and Taylor 1990b, Guan et al 1992 is performed on-chip. The pRAM uses a 1-µm CMOS gate-array with 39 000 gates.…”

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confidence: 99%

Digital integrated circuit implementations

Beiu¹

Handbook of Neural Computation

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This section considers some of the alternative approaches towards modeling biological functions by digital circuits. It starts by introducing some circuit complexity issues and arguing that there is considerable computational and physiological justification that shallow threshold gate circuits are computationally more efficient than classical Boolean circuits. We comment on the tradeoff between the depth and the size of a threshold gate circuit, and on how design parameters like fan-in, weights and thresholds influence the overall area and time performances of a digital neural chip. This is followed by briefly discussing the constraints imposed by digital technologies and by detailing several possible classification schemes as well as the performance evaluation of such neurochips and neurocomputers. Lastly, we present many typical and recent examples of implementation and mention the 'VLSI-friendly learning algorithms' as a promising direction of research.

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confidence: 99%

Digital integrated circuit implementations

Beiu¹

Handbook of Neural Computation

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The pRAM: an adaptive VLSI chip

Clarkson

Guan

1993

IEEE Trans. Neural Netw.

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The pRAM (probabilistic RAM) is a nonlinear stochastic device with neuron like behavior. The pRAM is realizable in hardware, and the third-generation VLSI pRAM chip is described. This chip is adaptive since learning algorithms have been incorporated on-chip, using reinforcement training. The pRAM chip is also adaptive with respect to the interconnections between neurons. Results achieved from a small net of pRAM's performing a pattern-recognition task using reinforcement training are presented.

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The application of noisy reward/penalty learning to pyramidal pRAM structures

Cited by 2 publications

References 3 publications

Digital integrated circuit implementations

Digital integrated circuit implementations

The pRAM: an adaptive VLSI chip

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