The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

Abstract

Post breakdown (BD) reliability is an important areaof study in ultra-thin gate dielectrics as it has significant implications on the performance degradation, lifetime, reliability margin and power dissipation of advanced sub-22 nm transistors and circuits. A prolonged phase of post-BD can ensure we can live with the circuit with moderate performance and error-free operation, even if the soft breakdown (SBD) events occur early. While analysis of post-BD is simple and straightforward for single layer SiO 2 / SiON stacks, the number of possible scenarios of post-BD increases when analyzing high-κ -interfacial layer (HK-IL) based technology. This is because the sequence of BD (whether HK or IL fails first followed by the other one) and the competition between multiple SBD in one of these layers, dilative wear-out of a single SBD spot and the possibility of a successive localized BD above / below the HK/IL BD percolation spot (with or without metal filamentation) are all possible phenomena that can be classified as post-BD. The likelihood of occurrence of these various possibilities will determine the immunity of the stack to post-BD degradation. We will investigate each of these scenarios in detail in this work in order to provide a comprehensive assessment of post-BD reliability of state-of-the-art technology. Our analysis on a HK:IL = 25:12Ǻ stack supported by electrical, physical and modeling results provides clear evidence that circuit failure at operating conditions can only be due to multiple SBD events within the IL layer and that the HK is very robust and resilient to breakdown.

TDDB Mechanism in a-Si/TiO2 Nonfilamentary RRAM Device

“…For positive CVS (HRS), a single-shallow-slope Weibull distribution is observed, which is similar to the shallow one of the negative CVS. This voltage polarity dependence of breakdown and Weibull slopes have not been observed in the dielectrics in MIM capacitors or MOSFETs [11][12][13][19][20][21][22][23][24][25][26].…”

“…It is generally well accepted that a percolation path will be gradually formed during the stress through random defect generation, leading to an abrupt hard breakdown and the conventional single Weibull slope with good area scaling, as observed in thicker dielectric layers [19][20][21]. Bimodal slopes have also been reported in nanoscale dielectrics, and several different explanations have been provided [12,[22][23][24][25][26]. In dielectrics with grains and grain boundaries (GB) [22][23][24], the steep Weibull slope at the lower percentile was attributed to breakdown at GBs leading to early device failure, and the upper percentile was mostly related to grain breakdown.…”

“…The time-to-breakdown Weibull plot has been extensively used to analyze the dielectric breakdown mechanism [19][20][21]. In addition to the well accepted percolation model with random defect generation, further investigations have been carried out recently to explain the bimodal Weibull distribution observed in nanoscale dielectrics, for example, by the localized defect generation in grain boundaries of polycrystalline materials [22][23][24], defect clustering effect in SiO2 or high-k oxide materials [12], or different defect generation rates in dual dielectric layers [25,26]. In this work, we will investigate the TDDB mechanism in non-filamentary a-VMCO by using the constant voltage stress (CVS) combined with Weibull plot and random telegraph noise (RTN) based defect profiling technique.…”

Reliability of emerging nanodevices

“…The physical defect signature for TDDB has been observed for various gate stacks using a high-resolution transmission electron microscope [35] to probe the defect site (shown by schematic in Figure 8.8(a)) [36]. As shown in Figure 8.7(b), the initial BD is very soft without any obvious physical defect detectable.…”

“…In the event of a catastrophic HBD, a physical morphology of the defect is observable (Figures 8.7 and 8.8). This could be due to either a complete oxygen depletion in the percolation core leading to silicon (for SiO 2 ) / hafnium (for HfO 2 ) nanowire formation in the oxide (Figure 8.8(d)) or a silicon epitaxial protrusion into the dielectric (Figure 8.8(e)) [35] (due to joule heating and thermomigration [40]) or spiking of the metal from the gate into the oxide (for nickel [38]-and tantalum [33]-based gate electrodes), resulting in a metal filament in the dielectric (Figure 8.8(f) and (g)) making the transistive action "non-existent." Another mechanism that affects the V TH value (and hence the drain (drive) current and transconductance as well) as a function of time is called negative bias temperature instability (NBTI) [41], which occurs most frequently in PMOS devices when biased in the inversion regime of conventional operation.…”