The AIM Photonics MPW: A Highly Accessible Cutting Edge Technology for Rapid Prototyping of Photonic Integrated Circuits

Abstract

Silicon photonics has been heralded for a number of high technology fields, but access to a high quality technology has been limited to vertically integrated design/fabrication companies, or fabless companies with significant resources to engage high volume fabs. More recently, research and development hubs have developed and released process design kits and multi-project wafer programs to lower the barrier. We present the first silicon photonics multi-project wafer (MPW) service produced in a state-of-the-art 300 mm fabrication facility. The MPW service is enabled by a best-in-class process design kit (PDK) which allows designers to layout and obtain photonic integrated circuits (PICs) that work properly on the first run. The fabrication of these circuits is carried out at the SUNY Polytechnic Institute which operates a world class 300 mm cleanroom that, besides silicon photonics, develops sub-7 nm CMOS architectures. The industrial-level management of this facility and its equipment provides high quality photonic devices which are repeatable from run-to-run along with rapid turnaround time. The devices that are available to designers via the process design kit are produced by Analog Photonics and have been verified on actual runs. The performance of these devices is comparable to the state-of-the-art and enables a wide variety of silicon photonic applications. Index Terms-Photonic integrated circuits, silicon photonics, foundries. I. INTRODUCTION O VER the past twenty years the popularity of silicon photonic integrated circuits (PICs) has increased as their reported performance improves. This popularity is partially driven due to the potential cost benefits that silicon-based PICs possess over alternative material platforms (ie, III-V). Specifically, PICs fabricated using a silicon-based platform are able to take advantage of the unsurpassed infrastructure of silicon-based electronic Manuscript

A Complete Si Photonics Platform Embedding Ultra-Low Loss Waveguides for O- and C-Band

“…To our knowledge, these propagation loss values are the best ever reported for single mode silicon waveguides in O and C bands [10], [23], [24] at the exception of [9] where strip waveguides patterned using immersion lithography show 0.4dB/cm loss in the C-band. The next important question is then to evaluate the impact of this annealing on more complex devices.…”

“…SiN enables to benefit from a lower optical index and low losses [15]- [17], but this solution only works for passive circuits. Some groups have shown very good results using a high resolution immersion lithography [9], [10], [18], but the fabrication cost is substantially higher. Another route is to smooth out the sidewalls using H2 thermal annealing.…”

Programmable photonic circuits

“…Multilayer threedimensional (3D) architectures can increase circuit complexity, flexibility and performance, and reduce footprint. Demonstrated multilayer Si photonic platforms have added integrated silicon nitride (SiN) [46], [49]- [51] or amorphous silicon layers [52] , vertically routeing light using low-loss adiabatic tapers. Such layers allow waveguide crossings with ultra-low-loss and cross-talk [49].…”

Inverse-Designed Photonics for Semiconductor Foundries

“…As discussed in the main text, the designs were fabricated on an AIM Photonics 300 mm wafer multi-project wafer (MPW) run. 23 We waived the minimum width DRC (design-rule check) rule for the spatial mode multiplexer, 50-50 directional coupler, and wavelength demultiplexer, and waived the minimum separation rule for the spatial mode multiplexer and wavelength demultiplexer. However, the designs were all successfully resolved by the 193 nm immersion lithography used in the AIM Photonics process, which can produce features as small as 40 nm across.…”