The advent of 3-D package age

Wu, L.; Wang, Yu-Po; Kee, S.C.; Wallace, Bruce; Hsiao, C.S.; Yeh, Clement; Her, T.D.; Lo, R.

doi:10.1109/iemt.2000.910714

Cited by 8 publications

(2 citation statements)

References 2 publications

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“…On the one hand, 3-D packaging can increase the electronic system's density, performance and reduce the cost of package. On the other hand, the high packaging efficiency of 3-D stacking leads to the high concentration of heat producing elements, resulting in a very high heat flux at the chip/package level [1], [2]. Usually, the concept of power density is used to identify the heat dissipation level of an IC package, which refers to the amount of power dissipated from per unit area of a chip, and it is usually expressed in units of watts per square centimeter (W/cm 2 ).…”

Section: Introductionmentioning

confidence: 99%

Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules

Tang¹,

Tan

Khan

et al. 2010

IEEE Trans. Comp. Packag. Technol.

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In this paper, an integrated liquid cooling system for 3-D stacked modules with high dissipation level is proposed. The fluidic interconnects in this system are elaborated and the sealing technique for different fluid interfaces is discussed. Meanwhile, the pressure drop for each part of the system is analyzed. The optimized fluidic interconnects minimizing the pressure drop have been designed and fabricated, and the compact system is integrated. In line with the fluidic interconnect design and analysis, an experimental process for hydraulic characterization of the integrated cooling system is established. The pressure drops for different fluidic interconnects in this system are measured and compared with the analyzed results.

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Section: Introductionmentioning

confidence: 99%

Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules

Tang¹,

Tan

Khan

et al. 2010

IEEE Trans. Comp. Packag. Technol.

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“…On the other hand, the high packaging efficiency of 3D stacking leads to the concentration many heat producing elements in a small volume, resulting in very high flux. [1] The power density of a single chip packaging is incessantly increasing and is expected to be higher than 100 W/cm 2 for high performance systems, such as defense systems.…”

Section: Introductionmentioning

confidence: 99%

3D packaging with through ilicon via (TSV) for electrical and fluidic interconnections

Khan

et al. 2009

2009 59th Electronic Components and Technology Conference

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In this paper a liquid cooling solution has been reported for 3-D package in PoP format. The high heat dissipating chip is mounted on a silicon carrier, which has copper through-silicon via for electrical interconnection and throughsilicon hollow via for fluidic circulation. Heat enhancement structures have been embedded in the chip carrier. Cooling liquid, de-ionized water is circulated through the chip carrier and heat from the chip is extracted. The fluidic channels are isolated from electrical traces using hermetic sealing. The research work has demonstrated 100 W of heat dissipation from one stack and total of 200 W from two stacks of the package. The fluidic interconnections and sealing techniques have been discussed.

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