The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Abstract

With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave) wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC) and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

Scalable THz Network-On-Chip Architecture for Multichip Systems

“…Ganguly et al [24] discussed the advances and challenges of interconnecting a multichip system with millimeter-wave wireless interconnects including interconnection topology, physical layer, medium access control (MAC), and routing protocols.…”

The Potentials, Challenges, and Future Directions of On-Chip-Antennas for Emerging Wireless Applications—A Comprehensive Survey

“…However, the packaging in horizontal and vertical stacked configurations in AoCs give rise to several severe issues such as front and backside radiations that may affect the overall system performance [196]. The quilt packaging in AoCs, on the other hand, mitigates the issues with conventional packaging style, enable direct radiation into the air, and reduce path loss [197]. In addition, the choice of materials in packaging, technologies, and interconnection mechanisms between radio die and antenna are the key considerations for the AoCs' packaging.…”

“…In addition, the choice of materials in packaging, technologies, and interconnection mechanisms between radio die and antenna are the key considerations for the AoCs' packaging. A complete detail of the packaging issues can be found in [196], [197]. The details of few important practical applications for which AoC based wireless interconnects are suitable are given below.…”

Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

“…The explosive growth of on-chip interconnections puts obstacles and bottlenecks in the way of optimising cost and performance of today's integrated circuits by posing signal integrity issues, routing complexities, crosstalk, and design challenges [1][2][3]. Multiplevalued logic (MVL) is a viable solution for this problem [4].…”