The acceleration of turbo decoder on the newest GPGPU of Kepler architecture

Zhang, Yang; Zhang, Xing; Ling, Yuan; Liu, Cang; Wang, Qinglin

doi:10.1109/iscit.2014.7011900

Cited by 6 publications

(8 citation statements)

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“…Furthermore, our design overcomes a range of significant challenges related to topological mapping, data rearrangement and memory allocation. 3) We implement a PIVI Log-BCJR LTE turbo decoder on a GPGPU as a benchmarker, achieving a throughput of up to 8.2 Mbps, while facilitating the same BER as our SIMD FPTD having a window size of N /P = 32, which is comparable to the throughputs of 6.8 Mbps and 4 Mbps, demonstrated in the pair of state-of-theart benchmarkers of [13] and [17], respectively. 4) We show that when used for implementing the LTE turbo decoder, the proposed SIMD FPTD achieves a degree of parallelism that is between 4 and 24 times higher, representing a processing throughput improvement between 2.3 to 9.2 times as well as a latency reduction between 2 to 8.2 times.…”

Section: Introductionmentioning

confidence: 89%

“…However, [12] and [42] demonstrated that turbo decoding is the most processor-intensive operation of basestation processing, requiring at least 64% of the processing resources used for receiving a message frame, where the remaining 36% includes the FFT, demapping, demodulation and other operations. Motivated by this, a number of previous research efforts [13], [14], [17], [18], [21], [38], [39], [43]- [45] have proposed GPGPU implementations dedicated to turbo decoding, as shown in Figure 3. Additionally, the authors of [27]- [30], [36], [40], [46], and [47] have proposed GPGPU implementations of LDPC decoders.…”

Section: Gpu Computing and Implementationsmentioning

confidence: 99%

“…In order to mitigate the inherent bottleneck that the serial nature of the Log-BCJR algorithm imposes on the achievable processing throughput, the above-mentioned GPGPU implementation of [13] invoke a variety of methods for increasing the parallelism of the algorithm. For example, the windowing technique of [17], [18] decomposes each frame of N bits into P equal-length windows, giving a window length of W = N P , as shown in Figure 1. The processing throughput may be increased by a factor of P upon processing the windows concurrently, each using separate forwards and backwards recursions.…”

Section: Introductionmentioning

confidence: 99%

“…The processing throughput may be increased by a factor of P upon processing the windows concurrently, each using separate forwards and backwards recursions. Here, the Previous Iteration Value Initialization (PIVI) technique of [17] and [18] may be employed for allowing the adjacent windows to assist each others' operation. However, the error correction capability of the PIVI Log-BCJR turbo decoder is degraded as the number P of windows is increased.…”

Section: Introductionmentioning

confidence: 99%

“…However, the error correction capability of the PIVI Log-BCJR turbo decoder is degraded as the number P of windows is increased. For this reason, the maximum number of windows employed in previous GPGPU implementations of the LTE turbo decoder associated with N = 6144 was P = 192 [13], [17], [18], which avoids any significant error correction performance degradation and facilitates a 192-fold increase in the grade of parallelism [19]. Further-more, the concept of trellis state-level parallelism may be employed [12].…”

Section: Introductionmentioning

confidence: 99%

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Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

et al. 2016

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Turbo codes comprising a parallel concatenation of upper and lower convolutional codes are widely employed in the state-of-the-art wireless communication standards, since they facilitate transmission throughputs that closely approach the channel capacity. However, this necessitates high processing throughputs in order for the turbo code to support real-time communications. In the state-of-the-art turbo code implementations, the processing throughput is typically limited by the data dependences that occur within the forward and backward recursions of the Log-BCJR algorithm, which is employed during turbo decoding. In contrast to the highly serial Log-BCJR turbo decoder, we have recently proposed a novel fully parallel turbo decoder (FPTD) algorithm, which can eliminate the data dependences and perform fully parallel processing. In this paper, we propose an optimized FPTD algorithm, which reformulates the operation of the FPTD algorithm so that the upper and lower decoders have identical operation, in order to support single instruction multiple data operation. This allows us to develop a novel general purpose graphics processing unit (GPGPU) implementation of the FPTD, which has application in software-defined radios and virtualized cloud-radio access networks. As a benefit of its higher degree of parallelism, we show that our FPTD improves the higher processing throughput of the Log-BCJR turbo decoder by between 2.3 and 9.2 times, when employing a high-specification GPGPU. However, this is achieved at the cost of a moderate increase of the overall complexity by between 1.7 and 3.3 times.INDEX TERMS Fully-parallel turbo decoder, parallel processing, GPGPU computing, software defined radio, could radio access network.

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Section: Introductionmentioning

confidence: 89%

Section: Gpu Computing and Implementationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

et al. 2016

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An efficient CPU‐GPU hybrid parallel implementation for DVB‐RCS2 receiver

Wang

et al. 2018

Concurrency and Computation

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The second-generation digital video broadcasting return channel via satellite (DVB-RCS2) is a promising real-time wireless protocol that has been widely used in many applications, such as video conferences, video feeds, and video multicasting. However, the receiver end of DVB-RCS2 is time consuming and should be accelerated by high-performance processing systems. Today, graphic processing units (GPUs) have been applied in communication systems due to high parallel capability and processing throughput. In this study, we design a novel pipeline of the receiver on the CPU-GPU platform. Moreover, we propose a CPU-GPU hybrid strategy to fully utilize resources and reduce communication latency. Compared with the parallel turbo decoder proposed in other work on the same platform, our parallel implementation achieves higher throughput. For the entire DVB-RCS2 receiver, compared with the non-pipelined serial and non-pipelined parallel algorithms, our proposed pipeline obtains 20 times and 6 times speedup, respectively.In addition, the latency of our implementation is lower than that of non-pipelined CPU-GPU implementation, which is equal to 1.06 ms. KEYWORDSCPU-GPU hybrid platform, pipeline, real-time receiver, software defined radio INTRODUCTIONOver the past decade, digital video broadcasting return channel via satellite (DVB-RCS) and its second generation, DVB-RCS2, have gained rapid prominence and support from governments and industries due to low-cost, high-performance, and reliable internet protocol (IP) networks through very small aperture terminals (VSATs). DVB-RCS2 specifies new technology that provides significant advances in time division multiple address (TDMA) performance for improved efficiency, increased throughput, and greater network reliability than DVB-RCS. DVB-RCS2 provides solutions for high-speed Internet access, video services, voice over IP, and global system for mobile communication backhaul used by the maritime industry, energy sector, utility companies, and global corporations. To the best of our knowledge, all services supported by DVB-RCS2 need low latency and high throughput and must provide real-time capability. Although the receive throughput of DVB-RCS2 is important, it cannot achieve high performance on a CPU platform. The graphic processing unit (GPU) provides a new platform to accelerate the wireless applications in software-defined radio. Compared to a CPU, GPU is a highly parallel, multi-threaded, multi-core processor with tremendous computational power and very large memory bandwidth. Thus, GPU is suitable in performing computation-intensive and highly parallel tasks.For convenience, we use the demodulator to represent all modules of the receiver except for the turbo decoder, as shown in Figure 2. By analyzing the running time of each part on the receiver, we find that the decoder is the most time-consuming part, so it has to be accelerated on the CPU-GPU platform. In fact, numerous studies have focused on how to accelerate the turbo decoder using the CPU-GPU platform. [1][2][3][4][5]...

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Low-latency and high-throughput software turbo decoders on multi-core architectures

Gal

Jégo

2019

Ann. Telecommun.

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The acceleration of turbo decoder on the newest GPGPU of Kepler architecture

Cited by 6 publications

References 8 publications

Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

An efficient CPU‐GPU hybrid parallel implementation for DVB‐RCS2 receiver

Low-latency and high-throughput software turbo decoders on multi-core architectures

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