Low-latency and high-throughput software turbo decoders on multi-core architectures

Gal, Bertrand Le; Jégo, Christophe

doi:10.1007/s12243-019-00727-5

Cited by 6 publications

(3 citation statements)

References 39 publications

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“…Since the emulation of FF operations requires a large number of instructions 21 (thus slowing down the performance of the processor), some researchers decided to use extremely powerful GPPs and/or graphical processing units (GPUs). However, even this very expensive approach has not proven to be applicable [22][23][24][25] in future communication networks (Table 3). Unlike FF-based codes, IECCs are perfectly suited for implementation on 64-bit processors.…”

Section: Discussionmentioning

confidence: 99%

Logarithmic time encoding and decoding of integer error control codes

Radonjić

Vujičić

2023

Engineering Reports

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One of the most important characteristics of all error control codes (ECCs) is the complexity of the encoding/decoding algorithms. Today, there are many ECCs that can correct multiple bit errors, but at the price of high encoding/decoding complexity. Among the rare exceptions are integer ECCs (IECCs), whose serial encoding/decoding algorithms run in O(n) time, where n is the codeword length. In this article, we show that IECCs can be encoded/decoded even faster, that is, that their parallel encoding/decoding algorithms have O(log2n) time complexity.

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Section: Discussionmentioning

confidence: 99%

Logarithmic time encoding and decoding of integer error control codes

Radonjić

Vujičić

2023

Engineering Reports

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“…Each one of the twin decoders run in the opposite direction to deliver the LLRs faster to the other decoders. Parallel decodable turbo codes are presented in [13]- [17]. The information bits here are divided into multiple groups, each of which is encoded separately and then multiplexed.…”

Section: Deploying Parallel Decodingmentioning

confidence: 99%

Combining serial and parallel decoding for turbo codes

AlMahamdy

Al-Falahy²

2021

IJEECS

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Reducing the decoding latency of the turbo codes is important to real-time applications. Conventionally, the decoding of the turbo codes (TC) runs in serial fashion, which means only one of the constituent soft decoders runs at a time. Parallel decoding (PD) refers to running the soft decoders in parallel. Although it delivers the output faster (compared to the serial decoding (SD)), it affects the bit- and frame-error rates. This paper proposes a decoding procedure that combines both PD and SD. It bridges the two decoding modes to determine the best combination scheme to achieve the required level of performance at an acceptable decoding latency. Presented results show how this procedure can mitigate the performance degradation at a slight increase in the decoding latency.

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“…Many SDR elementary blocks have been optimized for Intel® and ARM® CPUs. High throughput results have been achieved on GPUs; 19‐23 latency results are is still too high however to meet real time constraints and to compete with CPU implementations 22,24‐33 . This is mainly due to data transfers between the host (CPUs) and the device (GPUs), and to the nature of GPU designs, which are not optimized for latency efficiency.…”

Section: Introductionmentioning

confidence: 99%

A DSEL for high throughput and low latency software‐defined radio on multicore CPUs

Cassagne¹,

Tajan

Aumage

et al. 2023

Concurrency and Computation

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SummaryThis article presents a new Domain Specific Embedded Language (DSEL) dedicated to Software‐Defined Radio (SDR). From a set of carefully designed components, it enables to build efficient software digital communication systems, able to take advantage of the parallelism of modern processor architectures, in a straightforward and safe manner for the programmer. In particular, proposed DSEL enables the combination of pipelining and sequence duplication techniques to extract both temporal and spatial parallelism from digital communication systems. We leverage the DSEL capabilities on a real use case: a fully digital transceiver for the widely used DVB‐S2 standard designed entirely in software. Through evaluation, we show how proposed software DVB‐S2 transceiver is able to get the most from modern, high‐end multicore CPU targets.

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Low-latency and high-throughput software turbo decoders on multi-core architectures

Cited by 6 publications

References 39 publications

Logarithmic time encoding and decoding of integer error control codes

Logarithmic time encoding and decoding of integer error control codes

Combining serial and parallel decoding for turbo codes

A DSEL for high throughput and low latency software‐defined radio on multicore CPUs

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