The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware

Phase unwrapping is the process of converting discontinuous phase data into a continuous image. This procedure is required by any imaging technology that uses phase data such as MRI, SAR or OQM microscopy. Such algorithms often take a significant amount of time to process on a general purpose computer, rendering it difficult to process large quantities of information. This paper compares implementations of a specific phase unwrapping algorithm known as Minimum L P norm unwrapping on a Field Programmable Gate Array (FPGA) and on a Graphics Processing Unit (GPU) for the purpose of acceleration. The computation required involves a matrix preconditioner (based on a DCT transform) and a conjugate gradient calculation along with a few other matrix operations. These functions are partitioned to run on the host or the accelerator depending on the capabilities of the accelerator. The tradeoffs between the two platforms are analyzed and compared to a General Purpose Processor (GPP) in terms of performance, power and cost.

show abstract

“…In this section we discuss how the 1D DCT presented in [23] is extended to 2D. The DCT, similar to the FFT, is separable.…”

Section: Fpga Implementationmentioning

confidence: 99%

Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison

Braganza

Leeser

2008

2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications

Self Cite

View full text Add to dashboard Cite

show abstract

“…Swapping the real and imaginary parts of input and output data of DFT gives the IDFT operation. The authors in [18] used the similarity property between DFT and DCT equations to implement a real DCT from the DFT. For 2D modes, the 1D mode is performed two times: one time in all rows of input frame then another time on the columns of the result.…”

Section: Basic Asip Reconfigurable Enginesmentioning

confidence: 99%

Design and implementation of application‐specific instruction‐set processor design for high‐throughput multi‐standard wireless orthogonal frequency division multiplexing baseband processor

All¹,

Hassan²,

Hamdy³

et al. 2015

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

The two implementation choices for the baseband part of wireless radios are the application-specific platforms (e.g. application-specific integrated circuits (ASICs)) and the programmable processors (e.g. digital signal processors (DSPs)). An application-specific instruction-set processor (ASIP) is a customised processor that bridges the gap between the two platforms. In this work, a novel implementation of the signal processing part of an orthogonal frequency division multiplexing (OFDM) baseband processor using three ASIPs is presented. The ASIPs provide novel architectures for the symbol chain, including fast Fourier transform, channel estimation subsystem and synchronisation subsystem. This design provides a close to DSPs level of flexibility, making it suitable for supporting all the modes of a large number of OFDM standards. In the meantime, the system maintains a performance level comparable to ASICs. This is demonstrated by providing post-layout results for 0.13 μm Taiwan semiconductor manufacturing company complementary metal-oxide semiconductor technology.

show abstract

“…For an NxN matrix, this results in an operation that has O(N 2 log 2 N ) complexity since each 1-D DCT transform is O (N log 2 N ). The 1-D DCT itself was performed using an FFT and the method described in [3] and the FPGA implementation has been previously discussed in [4]. Sequential 1-D DCTs are pipelined so that while one is being calculated, another one is being loaded into memory.…”

Section: Samplementioning

confidence: 99%

An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware

Braganza

Leeser

2008

2008 16th International Symposium on Field-Programmable Custom Computing Machines

Self Cite

View full text Add to dashboard Cite

The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware

Cited by 7 publications

References 7 publications

Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison

Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison

Design and implementation of application‐specific instruction‐set processor design for high‐throughput multi‐standard wireless orthogonal frequency division multiplexing baseband processor

An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware

Contact Info

Product

Resources

About