An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware

Braganza, S.; Leeser, Miriam

doi:10.1109/fccm.2008.56

Cited by 1 publication

(4 citation statements)

References 7 publications

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“…They are pathindependent. In addition, some techniques are able to provide solutions minimizing the number of phase discontinuities [13,14]. The proposed architecture is based on the region-referenced method.…”

Section: Resultsmentioning

confidence: 99%

“…In addition, these implementations are realized by different platforms. The proposed architecture and the implementations in [13,14,16] are based on iterative phase-unwrapping algorithms. As compared with these implementations, the proposed architecture has the lowest computation time.…”

Section: Resultsmentioning

confidence: 99%

“…It is interesting to note that the algorithms implemented by [13,14,16] belong to a family of algorithms using minimum norm techniques [1]. They are pathindependent.…”

Section: Resultsmentioning

confidence: 99%

“…The implementations presented in [13,14] are based on PCG [1,5] or minimum L P norm [1] with field programmable gate array (FPGA) [15] devices and graphic processing unit (GPU) platforms, respectively. The implementation proposed in [16] is based on Gauss-Seidel techniques [1,6] with GPU platforms.…”

Section: Introductionmentioning

confidence: 99%

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Region-referenced phase unwrapping architecture for digital holographic microscopy

2014

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This work presents a novel hardware phase-unwrapping architecture for digital holographic microscopy. The architecture is based on an iterative region-referenced algorithm because of its simplicity and effectiveness for phase unwrapping. The architecture therefore consumes fewer hardware resources for very large-scale integration implementation. In addition, a novel data reuse scheme is adopted for reducing the memory bandwidth required by the architecture. The architecture can then have fast computation speed for the iterative operations. The architecture has been implemented by field programmable gate array. It acts as a hardware accelerator in an embedded system developed by a network-on-chip platform for performance measurement. The superiorities of the proposed architecture have been confirmed by the experiments.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

“…It is interesting to note that the algorithms implemented by [13,14,16] belong to a family of algorithms using minimum norm techniques [1]. They are pathindependent.…”

Section: Resultsmentioning

confidence: 99%