Testing oriented analysis of CMOS ICs with opens

Investigation into voltage and process variation-aware manufacturing test

“…The main difficulty in testing for full open defects arises from the fact that the voltage on the victim net is a parameter which is influenced by the surrounding circuitry, such as neighbouring nets and transistor nodes of driven inputs as shown in Figure 4.1 and it is a gate-internal defect [75,76,77]. In [70], five floating gate open defects were found by diagnosis and none of them showed supply voltage-dependent behaviour.…”

“…Intra-gate opens have been studied in [75,76,77,78,71,79], and it has been reported that such defects can cause delay behaviour, can increase IDDQ and can cause static faulty logic behaviour [77]. The focus in Chapter 4 is on full open defects on interconnect, since most open defects occur on interconnect [80].…”

Localization and Electrical Characterization of Interconnect Open Defects

“…O PEN defects are responsible for a high percentage of failures in interconnect lines and, as a consequence, are becoming a frequent defect type affecting present complementary metal-oxide-semiconductor (CMOS) integrated circuits [1]- [5]. A break may occur during some of the manufacturing process steps, causing a discontinuity at any physical line otherwise designed to electrically connect the two endpoints (nodes) of the line.…”

Detection probabilities of interconnect breaks: an analysis

“…Maly (10) observed that an interconnect break affecting either the p-subcircuit or the n-subcircuit does not hinder the functional behavior of the circuit, except for some changes in the circuit delay. However, an break affecting both the p-subcircuit and the n-subcircuit affects the whole charging and discharging path between the ground and V dd planes and thus changes the logic function of the circuit.…”