Localization and Electrical Characterization of Interconnect Open Defects

Abstract

Abstract-

Single‐configuration fault detection in application‐dependent testing of field programmable gate array interconnects

“…The fault model assumed in this paper is different from the ones used in [2,7,8]. In this paper, interconnect testing is applied at run time on a periodic basis, so only stuck-at and bridging faults are considered (open faults are mostly because of defects [9,24]). The stuck-at-1 and stuck-at-0 faults cause a programmable switch to be closed and open permanently, irrespective of the control signal.…”

“…A different scenario occurs at run time; in this case, the fault model can be substantially different from the one generally assumed in previous works [2,[6][7][8], that is, stuck-at, open and all pairwise bridging faults. At deployment time, the interconnect is likely to be affected by bridging faults of larger cardinality (involving more than just two nets) than fabrication defects (such as open faults that can be detected at manufacturing [9,10]). In addition to the fault model, application-depended testing at run time must also consider that an additional number of test vectors could be used within a configuration, that is, while still reducing the number of configurations, full coverage can be still preserved using a larger number of vectors.…”

A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects

“…The fault model assumed in this paper is different from the ones used in [3] [6]. In this paper as interconnect testing is applied at run time on a periodic basis, only stuck-at and bridging faults are considered (open faults are mostly due to defects [7] [16]). The stuck-at-1 and stuck-at-0 faults cause a programmable switch to be closed and open permanently, irrespective of the control signal.…”

“…As for coverage, all stuck-at faults and bridging faults (of any cardinality) occurring in any of the branches of the net will be propagated to the output using the activated branch (as per the fault model presented in Section II). As for open faults, even though mostly applicable to manufacturing than run time test [7], this type of fault is covered (detected) only in the activated branch and the stem of the net, i.e. open faults on the branches are not necessarily covered.…”

“…stuck-at, open and all pairwise bridging faults. At deployment time, the FPGA interconnect is likely to be affected by bridging faults of larger cardinality (involving more than just two nets) than fabrication defects (such as open faults that can be detected at manufacturing [7]). In addition to the fault model, application testing at run time must also consider that an additional number of test vectors could be used within a configuration, i.e.…”