A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects

Abstract

This paper presents a new method for applicationdependent testing of SRAM-based FPGA interconnects at run time. This method utilizes new features related to the function for the programming of the LUTs, the utilization (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused) IOs of the FPGAs. A new LUT programming function is introduced; the proposed method retains the original interconnect configuration and modifies the function of the LUTs using the so-called 1-Bit Sum Function (1-BSF); the 1-BSF detects all possible stuck-at and bridging faults (of all cardinalities) by utilizing the all zeros' vector and a walking-1 test set. As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4), the proposed method results in a single test configuration with 100% coverage under the assumed fault model.

Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints

“…The ADT of interconnect resources attempt to cover all given types of faults on nets, the signal paths constructed from multiple interconnect resources [4,5,19,20,21,22], rather than test each resource individually. Test strategies are categorized into three major types, including coding-based algorithms [2,8,14,15,16,21], SAT/SMT-based algorithms [3,9,17], and ATPG-related approaches [6,9,11,23,24]. Coding-based algorithms generate binary value assignments to the nets in a CUT using deterministic coding algorithms.…”

Single‐configuration fault detection in application‐dependent testing of field programmable gate array interconnects

“…An extensive literature is available for fault detection of interconnects; these approaches can be initially differentiated as application-independent [11][12][13][14][15][16][17][18][19] and application-dependent [2,5,6,8,[20][21][22]. Independent of the type of testing approaches, they strive for a complete (100%) fault coverage with reduced number of test configurations (rather than the number of applied test vectors) that the FPGA must undertake for testing, because it is well known that the number of configurations is the dominant figure of merit for test complexity of FPGAs.…”

“…The NCD is converted to a text file from which the total number of LUTs L, and the number of nets connected to each LUT I are determined. Within this process and compatible with previous approaches [1,2,7,8], the FFs and multiplexers are made transparent [22]. The pseudocode shown in Table 2 is used to implement the proposed algorithm for generating the single configuration in interconnect testing.…”

Low energy non-volatile look-up table using 2 bit ReRAM for field programmable gate array

“…Field-programmable gate arrays (FPGAs) are integrated circuits (ICs) that fill the niche in the market for low cost, fastdesign-and-debug cycles, and reduced time to market ICs with greater than 10× power efficiency of central processing units [1]. To implement combinational logic, conventional FPGAs devices like dynamic random-access memory (DRAM) and Flash in power consumption [3], endurance [4], and latency [5].…”