Testing of In-Memory-Computing 8T SRAMs

Tsai, Tsai-Ling; Li, Jin-Fu; Hsu, Chun-Lung; Sun, Chi-Tien

doi:10.1109/dft.2019.8875487

Cited by 21 publications

(15 citation statements)

References 20 publications

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“…To detect potential defects, Functional Fault Models (FFM) of a conventional SRAM memory can be used for testing the IMC in memory mode. March tests are widely used The test method proposed in [3] for an 8T SRAM-based IMC with NAND, NOR and XOR operations imposes two requirements:…”

Section: Incorrect Behavior R<20kωmentioning

confidence: 99%

“…Modifications have been made to the March C-test algorithm [2] in order to test IMC memory based on configurable 8T SRAM cells in both SRAM and TCAM operating modes. In summary, [2] and [3] proposed March-like test algorithms to test the proper IMC operation of 8T SRAM memories. However, these March algorithms do not cover all defects that may affect the read port.…”

Section: Incorrect Behavior R<20kωmentioning

confidence: 99%

“…One of the most promising alternatives is to use In-Memory Computing (IMC) architectures [2] [3]. Beyond their classical storage function, these memory architectures aim at integrating extra logic in the memory array and in the periphery to circumvent the von Neumann bottleneck problem.…”

Section: Introductionmentioning

confidence: 99%

“…To the best of our knowledge, only two solutions for functional testing of IMC memories based on volatile 8T SRAM cells have been reported in the literature [2] [3]. In [2], authors propose a March-like test for an IMC memory with SRAM and TCAM functions.…”

Section: Introductionmentioning

confidence: 99%

“…The March-like test can fully cover simple functional faults in SRAM mode and comparison faults in TCAM mode. In [3], authors propose a March C−8 test algorithm to cover typical functional faults and process variation-induced faults of an 8T SRAM-based IMC. Although the above solutions allow to functionally test an IMC architecture in both memory and computing modes, none of them has considered the detection of potential defects in the read port of the IMC memory, which is the main part of an IMC that differs from conventional 6T SRAM architectures.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures

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et al. 2021

2021 16th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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In-Memory-Computing (IMC) paradigm has been proposed as an alternative to overcome the memory wall faced by conventional von Neumann computing architectures. IMC architectures proposed today are built either from volatile or non-volatile basic memory cells, but a common feature is that all of them are prone to manufacturing defects in the same way as conventional memories. In this paper, we propose to analyze the behavior of an IMC 8T SRAM cell in presence of defects located in the read port of the cell. A model of a basic IMC memory array has been set up to simulate the behavior of the cell in the two modes of operation: memory mode and computing mode. Resistive short defects were injected into the read port and then analyzed. Preliminary results show that these defects can severely impact the behavior of the 8T SRAM in memory mode as well as computing mode. The final goal of this study is to develop effective test algorithms for these defects.

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Section: Incorrect Behavior R<20kωmentioning

confidence: 99%