Testing High-Resolution ADCs With Low-Resolution/Accuracy Deterministic Dynamic Element Matched DACs

Jiang, Hanjun; Olleta, B.; Chen, Degang; Geiger, R.L.

doi:10.1109/tim.2007.903621

Cited by 26 publications

(21 citation statements)

References 28 publications

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“…The approach in [6], [7] is aimed at relaxing the linearity requirements on the ramp generator. It proposes to use of a low resolution DAC with redundant, poorly matched elements together with a Deterministic Dynamic Element Matching (DDEM) strategy in order to estimate the static characteristics of a high resolution ADC.…”

Section: Generationmentioning

confidence: 99%

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Design of an on-chip stepwise ramp generator for ADC static BIST applications

Renaud

Barragán

Mir

2015

2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)

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This work presents guidelines for the design of an on-chip ramp signal generator for static Built-In Self-Test (BIST) of ADCs. The proposed ramp generator is based on a fully-differential switched-capacitor (SC) integrator conveniently modified to produce a very small integration gain. The main nonidealities affecting the linearity of the generator are discussed on a practical implementation in a 65nm CMOS technology. Electrical simulation results at transistor level are provided to verify the feasibility and performance of the proposed approach.

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Section: Generationmentioning

confidence: 99%

“…It proposes to use of a low resolution DAC with redundant, poorly matched elements together with a Deterministic Dynamic Element Matching (DDEM) strategy in order to estimate the static characteristics of a high resolution ADC. The work in [6], [7] demonstrates that a DDEM 8-bit DAC can be used to test a 12-bit ADC.…”

Section: Generationmentioning

confidence: 99%

Design of an on-chip stepwise ramp generator for ADC static BIST applications

Renaud

Barragán

Mir

2015

2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)

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“…In [13]- [16], the authors propose dynamic element matching and deterministic dynamic element matching test algorithms that allow histogram testing of higher resolution ADCs using lower resolution/imprecise DACs. These methods reduce or eliminate the nonlinearity of the DAC outputs before using them to test the ADC.…”

Section: Prior Workmentioning

confidence: 99%

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Kook

Choi

Chatterjee

2013

IEEE Trans. VLSI Syst.

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A low-cost linearity test methodology for high-resolution analog-to-digital converters (ADCs) is presented in this paper. Linearity testing of ADCs requires high-precision digital-to-analog conversion (DAC) capability, commonly 3-bit higher resolution than the ADC under test. Further, a large number of ADC output data samples must be collected making conventional histogram testing impractical for high-resolution ADCs with 18-24 bit precision. In the proposed test methodology, two low-precision and low-cost DACs are used to generate a high-resolution ADC test stimulus. Significant reductions in test cost and test time are achieved by using low-cost instrumentation and by making fewer measurements than required for conventional histogram test. A least-squares-based polynomial fitting approach is used to determine the transfer function of the ADC under test. The generated transfer function is used to compute the non-linearity of the ADC accurately. No assumption is made regarding the linearity of the lower precision signal generators (DACs) used in the testing procedure. Software simulations and hardware experiments are performed to validate the proposed test methodology.Index Terms-Analog-to-digital converters (ADCs), automated test equipment (ATE), built-in-self-test (BIST), device under test (DUT), differential nonlinearity, digital-to-analog converters (DACs), integral nonlinearity.

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“…One way to relieve this influence is interleaving the original triangular signal and the shifted signal [6]. Fig.2.b shows the output triangular signal, in which the original triangular signal and the shifted signal are interlaced.…”

Section: Stimulus Generatormentioning

confidence: 99%

“…Several algorithms that allow low linear stimuli to be used in test of high linearity ADC were presented in [4]- [6]. Experimental results of first two papers showed that 16 bits ADC can be tested within reasonable accuracy using stimulus with only 7 bits linearity.…”

Section: Introductionmentioning

confidence: 99%

Stimulus generator for SEIR method based ADC BIST

Duan

Vasan

Zhao

et al. 2009

Proceedings of the IEEE 2009 National Aerospace &Amp; Electronics Conference (NAECON)

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Testing of ADC in SOC is a significant challenge since it usually has no connection to the outside. Built-in self-test (BIST) is regarded as a promising alternative to traditional test. Most reported ADC BIST research works try to replicate a production test scheme on chip. This approach requires input ramp with high linearity which is hard to achieve on chip. This paper investigates signal generator implementation issues of adapting stimulus error identification and removal method which was presented for production test into a practical ADC BIST solution. A stimulus generator using very small transistor count is presented. Extremely simple methods for generating small constant voltage level shifts are introduced and evaluated. Simulation results show that generated signals with less than 7 bits linearity, together with the simple level shifts, are able to test a 16-bit ADC to 16 bit accuracy level. These results demonstrate that accurate BIST of deeply embedded AMS blocks may be practically implemented on chip with very low overhead.

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Testing High-Resolution ADCs With Low-Resolution/Accuracy Deterministic Dynamic Element Matched DACs

Cited by 26 publications

References 28 publications

Design of an on-chip stepwise ramp generator for ADC static BIST applications

Design of an on-chip stepwise ramp generator for ADC static BIST applications

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Stimulus generator for SEIR method based ADC BIST

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