Testing Defects and Parametric Variations in RAMs

Sachdev, Manoj; Gyvez, José Pineda de

doi:10.1007/0-387-46547-2_5

Cited by 1 publication

(2 citation statements)

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“…Now, in order to find and from (6), we do an approximation for the simplicity of mathematical operations. Since , we assume that and replace with so that (3) and (6) reduce to (9) and (10) respectively. Here, is the same total charge as deposited by the double exponent current pulse given by (3).…”

Section: Proposed Critical Charge Modelmentioning

confidence: 99%

“…that may also vary, variability in , , and are the most prominent since they directly affect the transistor's current driving capability. The variability increases as technology advances in the nanometer scale, thereby affecting the performance and yield of nanometric SRAM [8], [9]. In addition, due to the high aspect ratio of nanometric technologies, SRAM cells can have defective contacts and vias that fail to properly connect two layers [10].…”

Section: Introductionmentioning

confidence: 99%

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An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs

Jahinuzzaman

Sharifkhani

Sachdev

2009

IEEE Trans. VLSI Syst.

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Scaling transistor size to the scale of the nanometer coupled with reduction of supply voltage has made SRAMs more vulnerable to soft errors than ever before. The vulnerability has been accentuated by increased variability in device parameters. In this paper, we present an analytical model for critical charge in order to assess the soft error vulnerability of 6T SRAM cell. The model takes into account the dynamic behavior of the cell and demonstrates a simple technique to decouple the nonlinearly coupled storage nodes. Decoupling of storage nodes enables solving associated current equations to determine the critical charge for an exponential noise current. The critical charge model thus developed consists of both NMOS and PMOS transistor parameters. Consequently, the model can estimate critical charge variations due to variability of transistor parameters and manufacturing defects, such as resistive contacts and vias. In addition, the model can serve as a tool to optimize the hibernation voltage of low-power SRAMs or the size of MIM capacitor per cell in order to achieve a target soft error robustness. Critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90-nm CMOS process with a maximum discrepancy of less than 5%.Index Terms-Critical charge, process-induced variability, soft error, SRAM.

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Section: Proposed Critical Charge Modelmentioning

confidence: 99%