Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
DOI: 10.1007/0-387-46547-2_5
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Testing Defects and Parametric Variations in RAMs

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(2 citation statements)
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“…Now, in order to find and from (6), we do an approximation for the simplicity of mathematical operations. Since , we assume that and replace with so that (3) and (6) reduce to (9) and (10) respectively. Here, is the same total charge as deposited by the double exponent current pulse given by (3).…”
Section: Proposed Critical Charge Modelmentioning
confidence: 99%
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“…Now, in order to find and from (6), we do an approximation for the simplicity of mathematical operations. Since , we assume that and replace with so that (3) and (6) reduce to (9) and (10) respectively. Here, is the same total charge as deposited by the double exponent current pulse given by (3).…”
Section: Proposed Critical Charge Modelmentioning
confidence: 99%
“…that may also vary, variability in , , and are the most prominent since they directly affect the transistor's current driving capability. The variability increases as technology advances in the nanometer scale, thereby affecting the performance and yield of nanometric SRAM [8], [9]. In addition, due to the high aspect ratio of nanometric technologies, SRAM cells can have defective contacts and vias that fail to properly connect two layers [10].…”
Section: Introductionmentioning
confidence: 99%