Testing and built-in self-test – A survey

A test set embedding approach based on twisted-ring counter with few seeds

“…That is, compared with [12], this work requires 83% less test application time on average. In [13], we proposed an original test-sequence-reduction scheme that reduce test application time 4 Org to test application time 4 ¼ (1ÀRed2)test application time 4…”

“…Built-in self-test (BIST) is a more preferable solution to SoC test than traditional external auto test equipments (ATEs) because test pattern generation and test response analysis are performed on chip [1][2][3][4]. The built-in hardware includes an on-chip test pattern generator (TPG), a test response analyzer (TRA) and a BIST controller (BC).…”

“…1 considers a six primary-input (PI) CUT with a deterministic test set containing three test cubes. According to the seed-selection algorithm in [13], t1 is chosen as the first candidate seed (111x 4 x 5 x 6 ). Then embeddability judging is performed until the first embeddable case is found.…”

A parameterized graph-based framework for high-level test synthesis

“…So the BILBO register must concurrently act as both RTPG and MISR. The register with this feature is called concurrent BILBO (CBILBO) [28]. Because of area and delay overhead of CBILBO, having self-adjacent register in the architecture should be avoided.…”

Simultaneous reduction in test data volume and test time for TRC-reseeding

“…According to a definition given in [1], [2], BIST is a design-fortest technique in which testing is accomplished through built-in hardware features without using automatic test equipment (ATE). This is achieved by including an on-chip test pattern generator [typically is a Linear Feedback Shift Register, (LFSR)] and a response [typically is a Multiple-Inputs Signature Register, (MISR)] analyzer.…”