Test Strategy Planning Using Economic Analysis

Dear, Ian; Dislis, C.; Ambler, A.P.; Dick, Jochen

doi:10.1007/978-1-4757-5048-5_2

Cited by 4 publications

(1 citation statement)

References 5 publications

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“…Many kinds of complex chips, especially system-on-chips need to be improved by effective manufacturing methodologies. In the past decade, economics models of chip and board level were proposed to Anthony P. Ambler Electrical and Computer Engineering University of Texas at Austin Austin, TX 78712 512-471-6179 ambler@mail.utexas.edu help manufacturers predict total cost calculated from the early design stage to the test stage of products [1,2,3]. In general, the economics model is also called cost model.…”

Section: Introductionmentioning

confidence: 99%

Cost Effective Test Planning for System-on-Chip Manufacture

Lee

Ambler

2006

2006 IEEE Autotestcon

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The test of chip has become an important issue as its complexity has been dramatically increased. Currently, system-onchip (SoC) is major product that can be used for many applications. Since the SoC is a chip designed by VLSI design techniques, its methodologies of design and test are similar to conventional chip manufacturing aspects. However, the complexity, developing procedures, and many other things are different from the case of the conventional chips. Thus, new test approach is needed for complex SoC. The proposed economics model for SoC helps the chip developers predict total cost of SoC development at the early design stage, and decide the strategy to test by costeffective way.

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Section: Introductionmentioning

confidence: 99%