2006 IEEE Design and Diagnostics of Electronic Circuits and Systems
DOI: 10.1109/ddecs.2006.1649583
|View full text |Cite
|
Sign up to set email alerts
|

Test Scheduling for SOC under Power Constraints

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Publication Types

Select...
4
1

Relationship

0
5

Authors

Journals

citations
Cited by 6 publications
(1 citation statement)
references
References 5 publications
0
1
0
Order By: Relevance
“…The goals of these approaches can be summarized in the following way: a) effective utilization of all sources (connections, buses, scan chains), b) reduction of test application time, c) keeping power consumption under the highest permitted value. Because the problem of test scheduling was found to be an NP hard problem [5], various simplifying or heuristic approaches are used, e.g., [6] [11] [13] typically operating over a graph representation of a problem, e.g., by means of a TCG (Test Compatibility Graph) or a TACG (Test Application Conflict Graph) [4] [27].…”
Section: Amentioning
confidence: 99%
“…The goals of these approaches can be summarized in the following way: a) effective utilization of all sources (connections, buses, scan chains), b) reduction of test application time, c) keeping power consumption under the highest permitted value. Because the problem of test scheduling was found to be an NP hard problem [5], various simplifying or heuristic approaches are used, e.g., [6] [11] [13] typically operating over a graph representation of a problem, e.g., by means of a TCG (Test Compatibility Graph) or a TACG (Test Application Conflict Graph) [4] [27].…”
Section: Amentioning
confidence: 99%