Test program generation for functional verification of PowerPC processors in IBM

Aharon, Aharon; Goodman, Dave; Levinger, M.; Lichtenstein, Yossi; Malka, Yossi; Metzger, Charlotte; Molcho, Moshe; Shurek, Gil

doi:10.1145/217474.217542

Cited by 133 publications

(76 citation statements)

References 4 publications

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“…The sequential approach was implemented using Genesys, a modelbased test-generator from IBM [5] that was used by STMicroelectronics for the verification of ST100 family and ST200 family VLIW designs [6]. A Genesys system includes an architectural-definition model, which normally describes the architectural specification of single instructions.…”

Section: Sequential Vliw Generationmentioning

confidence: 99%

“…We show that even this type of processor architecture deteriorates the quality of tests created by a sophisticated test generator [5] and results in post-silicon VLIW related bug escapes. We found that various methodological enhancements are ineffective and that a parallel test generation technique is required to tackle the architectural parallelism.…”

Section: Introductionmentioning

confidence: 96%

See 1 more Smart Citation

VLIW - a case study of parallelism verification

Adir

Arbetman

Dubrov

et al. 2005

Proceedings. 42nd Design Automation Conference, 2005.

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Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper we report on the verification of a Very Large Instruction Word processor. The verification team used a sophisticated test program generator that modeled the parallel aspects as sequential constraints, and augmented the tool with manually written test templates. The system created large numbers of legal stimuli, however the quality of the tests was proved insufficient by several post silicon bugs. We analyze this experience and suggest an alternative, parallel generation technique. We show through experiments the feasibility of the new technique and its superior quality along several dimensions. We claim that the results apply to other parallel architectures and verification environments.

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Section: Sequential Vliw Generationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 96%

VLIW - a case study of parallelism verification

Adir

Arbetman

Dubrov

et al. 2005

Proceedings. 42nd Design Automation Conference, 2005.

View full text Add to dashboard Cite

show abstract

“…DAC'04, June 7-11, 2004 large and complex designs. With dynamic verification, the verification is done by generating a massive amount of tests using random test generators [1,2,10], simulating the tests on the design, and checking that the design behaves according to its specification. Coverage [9] is often used to monitor the progress of the verification process and point to areas in the design that have not been properly tested.…”

Section: Introductionmentioning

confidence: 99%

Probabilistic regression suites for functional verification

Fine

Ziv

2004

Proceedings of the 41st Annual Design Automation Conference

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Random test generators are often used to create regression suites on-the-fly. Regression suites are commonly generated by choosing several specifications and generating a number of tests from each one, without reasoning which specification should be used and how many tests should be generated from each specification. This paper describes a technique for building high quality random regression suites. The proposed technique uses information about the probability of each test specification covering each coverage task. This probability is used, in turn, to determine which test specifications should be included in the regression suite and how many tests should be generated from each specification. Experimental results show that this practical technique can be used to improve the quality, and reduce the cost, of regression suites. Moreover, it enables better informed decisions regarding the size and distribution of the regression suites, and the risk involved.

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“…Unfortunately, design errors sometimes slip through this testing process due to the immense size of the test space. To minimize the probability of undetected errors, designers employ various techniques to improve the quality of verification including co-simulation [4], coverage analysis, random test generation [5], and model-driven test generation [6].…”

Section: Design Faultsmentioning

confidence: 99%