Test pattern generation for multiple stuck-at faults

Karkouri, Y.; Aboulhamid, E.M.; Cerny, Eduard

doi:10.1109/etc.1993.246557

Cited by 5 publications

(6 citation statements)

References 29 publications

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“…On the 3-level of the circuit, we have the function . After applying of the procedures (1) and ( 2), we have: (00), (01), (10) {(00), ( 01), ( 10), ( 11)} ( 10), ( 11), (10)…”

Section: Practical Partmentioning

confidence: 99%

“…In this article we will consider single damages of the stuck-at-fault (0/1) type, that mainly occur in digital combinational devices . To detect such faults, various methods and algorithms [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] are known, for example: Truth Table and Fault Vatrix method based on the Boolean derivatives (Boolean difference), the Path Sensitization method and the Searching D-Algorithm based on the test patterns (PODEM), Brach-and-Bount method, etc . However, the vast majority of them are based on an analytical approach and are characterized by their complexity and cumbersomeness of practical implementation, that grows with the increase with amount of variables .…”

Section: Introductionmentioning

confidence: 99%

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A Simple Stuck-at-faults Detection Method in Digital Combinational Circuits

Rytsar¹

2023

Control syst. comput.

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This paper considers the new method of detection (diagnostic) stuck-at-faults (0/1) in digital combinational circuits based on a numerical set-theoretical approach. Compared to known methods and algorithms, the proposed approach differs in simpler implementation of searching for vectors of test codes at arbitrary points of the studied logic circuit. A few simple set-theoretical operations and procedures are sufficient to determine the location and the type of a stuck-at-fault (0/1). This is evidenced by the presented examples of application of the proposed method, that are borrowed from the publications of well-known authors.

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“…On the 3-level of the circuit, we have the function . After applying of the procedures (1) and ( 2), we have: (00), (01), (10) {(00), ( 01), ( 10), ( 11)} ( 10), ( 11), (10)…”

Section: Practical Partmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Simple Stuck-at-faults Detection Method in Digital Combinational Circuits

Rytsar¹

2023

Control syst. comput.

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“…In [10], the target fault is considered as a single component of several MSAF, and the test is generated for that target fault regardless of the effects of other faults that might be present. Such a test is able to test all the multiple faults which contain…”

Section: Introductionmentioning

confidence: 99%

Synthesis of multiple fault oriented test groups from single fault test sets

Ubar

Kostin

Raik

2013

2013 8th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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A novel approach for testing and diagnosing of multiple faults is discussed. A definition of a test group is introdueed to eope with the problem of fault masking. The eonditions are introduced to prove that a test group is sufficient to avoid fault masking. A method is presented for generating test groups regarding fault masking. Unlike the traditional test approaches, we do not target the faults as test objectives. The goal is to verify the correctness of a part of the circuit. The whole test sequence is presented as a set of test groups where each group has the goal to identify the correctness of a selected part of a circuit. The method facilitates fault diagnosis in the presence of multiple faults. Experimental research investigates the feasibility of the method and shows a way for tradeoffs between the test cost and robustness of the test regarding multiple faults.

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“…This makes the selection of the multiple faults in such a way that the cumulative effect of all these faults make up the target fault. Hence, independent multiple faults could not be selected (Karkouri et al, 1993). Takahashi et al (1991) proposed an approach, where sets of multiple faults are represented as Boolean functions and shared BDDs are used as an internal representation of these functions.…”

Section: Introductionmentioning

confidence: 99%

“…However, as explained earlier, this may not be adequate for defects in modern devices with multiple faults. Karkouri et al (1993) proposed a technique where a target fault is taken, which is a single component of possibly several multiple faults. Test patterns are generated to propagate the effect of the target fault to primary outputs.…”

Section: Introductionmentioning

confidence: 99%

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

Anita

Sudheesh

2016

IJHPSA

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An algorithm of test pattern generation for multiple faults is proposed using the zero suppressed decision diagrams (ZBDDs). Test pattern generation plays a major role in the design and testing of any chip. The proposed ZBDD is generated from its corresponding binary decision diagram (BDD). A test ZBDD is obtained from the true and faulty ZBDDs and the test patterns are generated from the test ZBDD. The obtained patterns are reordered because the order in which these patterns are used to test the chip is immaterial as far as the faults are concerned but the transitions between the test patterns affect the test power. Hence, the primary objective of the proposed work is the generation of test patterns for a given set of multiple faults. The next objective is to reduce the test power which is the power consumed during testing.

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Test pattern generation for multiple stuck-at faults

Cited by 5 publications

References 29 publications

A Simple Stuck-at-faults Detection Method in Digital Combinational Circuits

A Simple Stuck-at-faults Detection Method in Digital Combinational Circuits

Synthesis of multiple fault oriented test groups from single fault test sets

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

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