Test Infrastructure for Address-Event-Representation Communications

Address-Event-Representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for neuro-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The information transmitted is a sequence of spikes coded using high speed digital buses. These multi-layer and multi-chip AER systems perform actually not only image processing, but also audio processing, filtering, learning, locomotion, etc. This paper present an AER interface for controlling an anthropomorphic robotic hand with a neuro-inspired system.

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“…The hardware based frame to AER conversion has been developed for another board under the project: the CAVIAR USB-AER board [6].…”

Section: Pci-aer Interfacementioning

confidence: 99%

“…The goal of this community is to build large multichip and multi-layer hierarchically structured systems capable of performing complex massively-parallel processing in real time. The success of such systems will strongly depend on the availability of robust and efficient development, debugging and interfacing AER-tools [6].…”

Section: Introductionmentioning

confidence: 99%

AER Neuro-Inspired interface to Anthropomorphic Robotic Hand

Linares-Barranco

Paz-Vicente

Jiménez

et al. 2006

The 2006 IEEE International Joint Conference on Neural Network Proceedings

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“…They achieve these purposes with a very high AER bandwidth, but with the necessity of a PC for Event processing purposes [7].…”

Section: Introductionmentioning

confidence: 99%

Address-event-based platform for bioinspired spiking systems

et al. 2007

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Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows a real-time virtual massive connectivity between huge number neurons, located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems, it is absolutely necessary to have a computer interface that allows (a) reading AER interchip traffic into the computer and visualizing it on the screen, and (b) converting conventional frame-based video stream in the computer into AER and injecting it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. In the other hand, the use of a commercial personal computer implies to depend on software tools and operating systems that can make the system slower and un-robust. This paper addresses the problem of communicating several AER based chips to compose a powerful processing system. The problem was discussed in the Neuromorphic Engineering Workshop of 2006. The platform is based basically on an embedded computer, a powerful FPGA and serial links, to make the system faster and be stand alone (independent from a PC). A new platform is presented that allow to connect up to eight AER based chips to a Spartan 3 4000 FPGA. The FPGA is responsible of the network communication based in Address-Event and, at the same time, to map and transform the address space of the traffic to implement a pre-processing. A MMU microprocessor (Intel XScale 400MHz Gumstix Connex computer) is also connected to the FPGA to allow the platform to implement eventbased algorithms to interact to the AER system, like control algorithms, network connectivity, USB support, etc. The LVDS transceiver allows a bandwidth of up to 1.32 Gbps, around ~66 Mega events per second (Mevps).

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“…This chain is composed by a 64 Â 64 retina that spikes with temporal and contrast changes [13], two convolution chips to detect a ball at different distances from the retina [23], an object chip to filter the convolution activity [18] and a learning stage composed by two chips: delay line and learning [11]. To make all this vision system possible, a set of AER tools for debugging and interconnection [19] purposes are not only useful, but also necessary. Fig.…”

Section: Caviar Scenariomentioning

confidence: 99%

“…A USB-AER board with a Spartan II 200 FPGA [19] has been used for the first random method implementation (without improvements), using images with all pixels to zero, except one, with different gray values. Another USB-AER board, configured as a datalogger [19] that captures events and their timestamp, controlled through MATLAB, has been also used to capture the ISIs. Fig.…”

Section: Inter-spike-intervals Distribution Analysismentioning

confidence: 99%

Inter-spike-intervals analysis of AER Poisson-like generator hardware

et al. 2007

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Address-Event-Representation (AER) is a communication protocol for transferring images between chips, originally developed for bio-inspired image-processing systems. Such systems may consist of a complicated hierarchical structure with many chips that transmit images among them in real time, while performing some processing (for example, convolutions). In developing AER-based systems it is very convenient to have available some means of generating AER streams from on-computer stored images. Rank order coding (ROC) and Poisson rate coding are the extremes of spikes coding. In this paper, we present a pseudo-random hardware method for generating AER streams in real time from a sequence of images stored in a computer's memory. The Kolmogorov-Smirnov test has been applied to quantify that this method follows a Poisson distribution of the spikes. A USB-AER board, developed by our RTCAR group, have been used for the measurements. An example scenario of use under the EU CAVIAR project is presented. r

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Test Infrastructure for Address-Event-Representation Communications

Cited by 21 publications

References 2 publications

AER Neuro-Inspired interface to Anthropomorphic Robotic Hand

AER Neuro-Inspired interface to Anthropomorphic Robotic Hand

Address-event-based platform for bioinspired spiking systems

Inter-spike-intervals analysis of AER Poisson-like generator hardware

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