Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines

Takahashi, Hiroshi; Higami, Yoshinobu; Kikkawa, Toru; Aikyo, Takashi; Takamatsu, Yasushi; Yamazaki, Koji; Tsutsumi, Toshiyuki; Yotsuyanagi, Hiroyuki; Hashizume, Masaki

doi:10.1109/dft.2007.11

Cited by 8 publications

(5 citation statements)

References 9 publications

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“…To evaluate the performance of the procedure presented in Sec.IV, we use full-scan version of ISCAS'89 benchmark circuits and the test patterns for detecting resistive open faults [8]. The number of adjacent lines is set to 5 for each line.…”

Section: Resultsmentioning

confidence: 99%

“…In this paper, we consider the resistive open fault model described in [8]. In this fault model, the additional delay of a line with resistive open fault depends on the delay caused by the resistive open defect and the signal transition(s) at the adjacent lines.…”

Section: Resistive Open Fault Modelmentioning

confidence: 99%

“…Completely open faults are modeled as logical faults, whereas resistive open faults are modeled as small delay faults at wires, contacts and/or vias of a circuit. In [8], we showed that the additional delay of the signal transition at a line with a resistive open fault is affected by the signal transition(s) at lines adjacent to this line. A number of small delay fault diagnosis methods have been proposed in [9]- [12].…”

Section: Introductionmentioning

confidence: 99%

“…A number of open fault models and their diagnosis have been proposed by various researchers [1]- [8]. Open faults are classified into two categories, namely completely open faults and resistive open faults.…”

Section: Introductionmentioning

confidence: 99%

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Diagnosing Resistive Open Faults Using Small Delay Fault Simulation

Yamazaki

Tsutsumi

Takahashi

et al. 2013

2013 22nd Asian Test Symposium

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Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant of the faulty line but it is also dependent on the signal transition(s) on its adjacent lines. In this paper, we propose an efficient simulation method to simulate small delay faults and we use this simulator to diagnose resistive open faults.The fault simulator developed by us simulates all delay faults for one signal line simultaneously. This information is then used to deduce the candidate faulty lines in two steps. Experimental results for ISCAS'89 benchmark circuits show that by using the method proposed by us the faulty lines can be identified correctly in most cases.

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Section: Resultsmentioning

confidence: 99%

Section: Resistive Open Fault Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Diagnosing Resistive Open Faults Using Small Delay Fault Simulation

Yamazaki

Tsutsumi

Takahashi

et al. 2013

2013 22nd Asian Test Symposium

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“…[5]. Also, we have proposed a test method and a diagnosis one for open defects occurring at interconnect lines [7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Output voltage estimation of a floating interconnect line caused by a hard open in 90nm ICs

Manabe

Yamada

Yotsuyanagi

et al. 2010

2010 10th International Symposium on Communications and Information Technologies

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Faulty effects caused by a hard open defect at an interconnect line in a 90nm CMOS IC are analyzed by device simulation in this paper. The simulation results reveal us that output voltage of the floating interconnect line is obtained as linear sum of effects from logic signals of the adjacent interconnect lines and the defective one. Also, an estimation model of voltage at the floating interconnect line is proposed. Feasibility of the estimation is examined in this paper. The result shows us that the voltage can be estimated within error of about 0.03V.

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