Test-architecture optimization for TSV-based 3D stacked ICs

Time-multiplexed test access architecture for stacked integrated circuits

“…The configurable options of each lane of the flexible parallel test bus include direction (In, Out or BiDir) and edge of clock for sending output (positive or negative). Generally, besides a sequential test access to each die, the test access optimization schemes can result in daisy-chained and/or parallel accesses [5,6,7]. Even though there is a separate TAP controller on each die of P1838 complied stack, all wrapped dies stay in a common state, e.g., shift, capture, update, because control signals are broadcast to them.…”

Test Planning for Core-based Integrated Circuits under Power Constraints

“…Various authors have discussed testing, test architecture design and optimization for non-stacked ICs with IEEE 1149.1 [1-3, 8-10, 21, 22, 27, 28, 31]. For SICs with TSVs, optimization of DfT architecture has also been addressed [17,20]. However, reduction of overall test cost for core based ICs supported by the IEEE 1149.1 test infrastructure, considering both test time and DfT hardware while meeting a power constraint, which remains unexplored, is addressed in this paper.…”

Scheduling Tests for 3D Stacked Chips under Power Constraints

“…3D TSV-SICs can be obtained by three stacking processes, viz, Die-toDie (D2D), Wafer-to-Wafer (W2W) and Die-to-Wafer (D2W). In W2W stacking, complete wafers are stacked over one another, resulting in exponentially decreasing yields with increasing number of layers in the stack [15]. Therefore, this paper considers D2W and D2D stacking [15].…”

“…Recent research have addressed test architecture design for 3D TSV-SICs [15], testing the TSVs [7-10, 15, 18] and 3D TSV-SIC specific defects [7,10]. Due to imperfections in IC manufacturing, traditionally, for non-stacked ICs, each individual chip was tested twice [1,14] in the following instances:…”