Teramac-configurable custom computing

Amerson, R.; Carter, R.J.; Culbertson, W. Bruce; Kuekes, Philip J.; Snider, Greg

doi:10.1109/fpga.1995.477406

Cited by 51 publications

(32 citation statements)

References 9 publications

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“…One of the most referenced examples related to fault tolerance of systems with a medium/high ratio of defective components is the reconfigurable architecture of TERAMAC designed by HP researchers [18]. In this example, a computer is organized from a reconfigurable structure made up of around 8 million components (220 thousand programmable logic cells, 145 thousand interchip elements and millions of crossbars).…”

Section: Successful Fault Tolerance Precedentsmentioning

confidence: 99%

Electronic System Design Paradigms in the Technologies of the Year 2020

García¹,

Moll²,

Rubio³

2010

Int.J.Soc.Mater.Eng.Resour.

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This paper analyses the evolution of late and beyond CMOS technologies showing the relevant effect on the electronic design methods and rules due to the dramatic reduction of quality of the manufactured components. The paper argues that the main impact on such future technologies will be caused by the increase of the manufacturing defect ratio of components and circuits, the reduction of reliability through a huge increase of the error ratio and a drastic drop of the components quality. Consequently, new strategies of design have to be considered, among them the hierarchical fault tolerance that is presented in the paper. This fact will have implications in the design rules as we know them today.

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Section: Successful Fault Tolerance Precedentsmentioning

confidence: 99%

Electronic System Design Paradigms in the Technologies of the Year 2020

García¹,

Moll²,

Rubio³

2010

Int.J.Soc.Mater.Eng.Resour.

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“…In a reconfigurable architecture, recovery entails isolating defective module(s) and incorporating spare structures as needed. Support for reconfiguration can be achieved at various granularities, from ultrafine grain systems [7,8] that have the ability to replace individual logic gates to coarser designs that focus on isolating entire processor cores [1,2,[9][10][11][12][13][14]21]. This choice presents a trade-off between complexity of implementation and potential lifetime enhancement [15,16].…”

Section: Related Workmentioning

confidence: 99%

Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

Kim

2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/ power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

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“…FPGAs consist of a matrix of ®ne grain computational elements, usually implemented using lookup tables, with a hierarchy of programmable interconnections. Although traditionally FPGAs have been used for logical design and hardware emulation, their suitability as computing engines for recon®gurable architectures has also been explored [1,19]. Research is also being carried out on the design of coarser grain architectures that incorporate recon®gurable features [20,23,27].…”

Section: Introductionmentioning

confidence: 99%

Dynamic reconfiguration of node location in wormhole networks

Sánchez

García

2000

Journal of Systems Architecture

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Several techniques have been developed to increase the performance of parallel computers. Recon®gurable networks can be used as an alternative to increase the performance. Network recon®guration can be carried out in di erent ways. Our research has focused on distributed memory systems with dynamic recon®guration of node location. Brie¯y, this technique consists of positioning the processors in the network depending on the existing communication pattern among them, to suit the requirements of each computation.In this article, we present a dynamic recon®guration technique for wormhole networks. We have used both a crossbar and a multistage interconnection network to implement a recon®gurable logical two-dimensional (2-D) torus topology. The recon®guration mechanism is based on a distributed recon®guration algorithm. The algorithm is based on a cost function that requires only local information. We discuss recon®guration features and adjust the di erent parameters of the recon®guration algorithm. We have also studied the deadlock problem in recon®gurable wormhole networks, and give details of our solution. Finally, we have evaluated the performance of this technique under several workloads. Ó

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Teramac-configurable custom computing

Cited by 51 publications

References 9 publications

Electronic System Design Paradigms in the Technologies of the Year 2020

Electronic System Design Paradigms in the Technologies of the Year 2020

Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

Dynamic reconfiguration of node location in wormhole networks

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