Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis

Chen, Shen‐Ming; Tang, Chi-Sun; Tsai, Sung-Fang; Tsai, Chen‐An; Chien, Shao-Yi; Chen, Liang-Gee

doi:10.1109/jssc.2010.2067910

Cited by 4 publications

(3 citation statements)

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“…( 1) was generated by multiplication of the accumulated value by i_C (3) and stored in r_Denominartor (1665). Finally, the GSLD score (10) was obtained by dividing the data stored in r_numerator by r_denominator. The average computation speed of the GSLD engine is 268 cycles (1.34 μs) per GSLD operation for the test case, which mainly includes the SBS calculation for each cluster and division to obtain the GSLD result.…”

Section: Lsi Implementation Of Proposed Gsld Enginementioning

confidence: 99%

“…[4][5][6][7] Many unsupervised clustering algorithms such as hierarchical clustering, K-means and self-organizing maps have been developed to realize the data categorization. [8][9][10] As the most widely used clustering algorithm in hardware implementation, K-means has advantages in its computational efficiency and clustering performance. However, it is critical to deal with the problems in clustering such as (i) how to automatically obtain the optimal cluster number and (ii) how to ensure the target objects in an image are well categorized based on their features.…”

Section: Introductionmentioning

confidence: 99%

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Highly accurate and efficient cluster validation index engine using global separation and local dispersion architecture for adaptive image clustering systems

Shen

Endoh

2021

Jpn. J. Appl. Phys.

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This paper presents a novel cluster validity index (CVI) engine based on global separation and local dispersion (GSLD) used to improve the accuracy and calculation efficiency of adaptive image clustering systems. The proposed GSLD engine can efficiently improve upon traditional GSLD calculation speed by making full leverage of temporary computation results obtained during the image clustering process itself. The CVI large-scale integrated (LSI) engine, designed with 55 nm CMOS technology, successfully achieves a 200 MHz GSLD calculation rate within 268 clocks using 8-bit data precision. In addition, by comparing various conventional CVI methods, the proposed CVI engine’s superiority is demonstrated by the deployment of real-life images and complex artificial datasets with different sizes, densities, and even overlaps. The experimental result reveals that the GSLD architecture’s computational complexity is reduced by 88.9% compared with the conventional variance ratio criterion (VRC) CVI and general GSLD calculation.

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Section: Lsi Implementation Of Proposed Gsld Enginementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Highly accurate and efficient cluster validation index engine using global separation and local dispersion architecture for adaptive image clustering systems

Shen

Endoh

2021

Jpn. J. Appl. Phys.

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“…The proposed object recognition processor has some characteristics of application specific hardware accelerators such as IMAPCAR [6] and National Taiwan University's machine learning SoC [9]. In these systems, a highly parallel SIMD architecture and a high bandwidth dual memory architecture are adopted to accelerate in-vehicle image recognition and K-means clustering algorithm respectively, restricting redundant data computations and memory accesses for their targeted applications.…”

Section: B Related Workmentioning

confidence: 99%

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Kim

Park

et al. 2013

IEEE J. Solid-State Circuits

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Abstract-A heterogeneous multi-core processor is proposed to achieve real-time dynamic object recognition on HD 720p video streams. The context-aware visual attention model is proposed to reduce the required computing power for HD object recognition based on enhanced attention accuracy. In order to realize real-time execution of the proposed algorithm, the processor adopts a 5-stage task-level pipeline that maximizes the utilization of its 31 heterogeneous cores, comprising four simultaneous multithreading feature extraction clusters, a cache-based feature matching processor and a machine learning engine. Dynamic resource management is applied to adaptively tune thread allocation and power management during execution based on the detected amount of tasks and hardware utilization to increase energy efficiency. As a result, the 32 mm chip, fabricated in 0.13 m CMOS technology, achieves 30 frame/sec with 342 8-bit GOPS peak performance and 320 mW average power dissipation, which are a 2.72 times performance improvement and 2.54 times per-pixel energy reduction compared to the previous state-of-the-art.Index Terms-Multi-core processor, object recognition, scale invariant feature transform, heterogeneous, low power processor, dynamic resource management, dynamic voltage and frequency scaling. GLOSSARY OF ABBREVIATIONS GOPS

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Embedded Intelligence: State-of-the-Art and Research Challenges

Seng

Ang

2022

IEEE Access

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Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis

Cited by 4 publications

References 20 publications

Highly accurate and efficient cluster validation index engine using global separation and local dispersion architecture for adaptive image clustering systems

Highly accurate and efficient cluster validation index engine using global separation and local dispersion architecture for adaptive image clustering systems

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Embedded Intelligence: State-of-the-Art and Research Challenges

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