Temperature Transients In Normal And Giant Magneto-resistance Memory Cells

Pohm, A.V.; Comstock, C.S.; Kohl, Clinton E.; Ranrnuthu, I.; Ranmuthu, K.T.M.

doi:10.1109/nvmt.1993.696936

Cited by 1 publication

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“…A theoretical calculation of these values is shown later in this section. Though a distributed multipole circuit might have been more accurate, observing the experimental thermal response [31], we intuitively assumed that a single-pole circuit would serve the purpose quite adequately [24]. However, if a single-pole circuit is not satisfactory, we can instead easily distribute the total thermal resistance and capacitance into a multipole circuit in our model.…”

Section: Main Circuit For a Generalized Pseudo-spin-valvementioning

confidence: 99%

Universal HSPICE macromodel for giant magnetoresistance memory bits

2000

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Nonvolatile semiconductor storage using giant magnetoresistance (GMR) memory bits has the potential for revolutionizing both high-density and high-speed memory applications with devices exhibiting unlimited write endurance and very low write energy. This paper presents the first universal circuit macromodel for GMR memory bits. The macromodel is realized as a four-terminal subcircuit that emulates GMR bit behavior over a wide range of sense and word-line currents. It realistically models the nonlinear and hysteretic behavior of GMR memory bits, their transient thermal behavior, and the sense-current dependency of their write thresholds. The model is flexible and relatively simple: Ranges of the write/read currents and bit resistance values are incorporated as parameterized variables, and no semiconductor devices are used within the model.

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Section: Main Circuit For a Generalized Pseudo-spin-valvementioning

confidence: 99%