Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective

Tayal, Shubham; Mittal, Vikas; Jadav, Sunil; Gupta, Shikhar; Nandi, Ashutosh; Krishan, Bal

doi:10.1016/j.cryogenics.2020.103087

Cited by 16 publications

(4 citation statements)

References 33 publications

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“…In this study, the effect of temperature change (between 300 and 500 K) on linearity analysis in nanotube junction-less surrounding gate (NT-SG) MOSFETs was examined using Silvaco 3D. [15][16][17][18] Section 2 provides details on the device fabrication and simulation setup. The influence of temperature on the linearity of the proposed model is examined in Section 3.…”

Section: Introductionmentioning

confidence: 99%

“…Analyzing the linearity figure of merits can assist in addressing this problem associated with wireless performance. In this study, the effect of temperature change (between 300 and 500 K) on linearity analysis in nanotube junction‐less surrounding gate (NT‐SG) MOSFETs was examined using Silvaco 3D 15–18 . Section 2 provides details on the device fabrication and simulation setup.…”

Section: Introductionmentioning

confidence: 99%

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Impact of temperature variation on linearity parameters of nanotube surrounding gate (NT‐SG) MOSFETs

Garg,

Pandey,

Pandey

et al. 2023

Int J Numerical Modelling

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The work investigates the effect of temperature variation on the linearity performance of Nanotube Junctionless Surrounding Gate (NT‐SG) MOSFET. In this study, the linearity parameters of NT‐SG MOSFET is investigated by changing the temperature range from 300 to 500 K using the Silvaco 3D Simulator. For the specified temperature range, characteristics including high‐order trans‐conductance (gm2 and gm3), IIP3, VIP3, and VIP2 have been assessed. All of these metrics exhibit great linearity and little distortion at the NT‐SG MOSFET's zero crossover point for Vds = 0.01 V. The VIP2 and VIP3 are found to be increased when the temperature range increases from 300 to 500 K and thus the device is found to be more suitable for high‐frequency applications. In addition to this, the NT‐SG MOSFET manifests enhanced analog performance and is also more immune toward SCEs.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Impact of temperature variation on linearity parameters of nanotube surrounding gate (NT‐SG) MOSFETs

Garg,

Pandey,

Pandey

et al. 2023

Int J Numerical Modelling

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“…Due to its interband tunneling current transfer mechanism, the device has been getting attracted by researchers in the last decade [5]. Recently, structural modification and material selection are the critical parameters for developing TFET technology [6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of a double gate SiGe/Si tunnel FET with unique inner-gate engineering

Dash¹,

Mishra²

2022

Semicond. Sci. Technol.

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An inner-gate engineered double gate heterostructure TFET (SiGe/Si-IGTFET) has been presented. The inner-gate is grown at the center of the Si0.6Ge0.4/Si TFET, followed by a thin HfO2 dielectric layer. The drain current performance of the suggested device has been investigated comprehensively to discover its efficacy. The device provides much-lower ambipolarity (by 6-decades) compared to heterostructure TFET with a similar dimension. The SiGe/Si-IGTFET device has also shown higher immunity against short channel effects such as drain induced barrier lowering (DIBL) and gate induced drain leakage current (IGIDL). To examine the impact of inner-gate, various DC parameters such as ambipolar current (Iamb), on current (Ion), Ion/Iamb current ratio, average subthreshold swing (SS), surface potential, and electric field have been considered. The device offers a much improved current ratio (Ion/Iamb) of 1.78×1012 with an average SS of 23 mV/decade by optimizing the position and dielectric material of the inner-gate. The simulation of the suggested device is carried out using a 2-D Silvaco Technology Computer-Aided Design (TCAD) device simulator.

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“…The temperature has a profound influence on the effective performance of nanodevices attributable to a diverse set of temperature-sensitive electronic applications such as defense, transportation, nuclear industry, telecommunication networks, satcoms, aerospace, IR sensor, and terrestrial devices. 24,25 Consequently, the need for investigating the performance of vertically stacked NSFET at various temperatures is a requisite. Further, for constant electric field scaling, gate oxide needs to be scaled down in the same proportion.…”

mentioning

confidence: 99%

Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node

Valasa¹,

Tayal²,

Thoutam³

2022

ECS J. Solid State Sci. Technol.

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This paper demonstrates the impact of temperature variation on vertically stacked junctionless nanosheet field effect transistor (JL-NSFET) concerning analog/RF performances using different gate lengths (Lg) along with high-k gate dielectrics. A comprehensive analysis of analog/RF performances like transconductance (gm), gate capacitance (Cgg), gate to drain capacitance (Cgd), output conductance (gds), intrinsic gain (Av), maximum oscillation frequency (fMAX), gain frequency product (GFP), and cutoff frequency (fT) is carried out for the temperature range 77-400 K. Note that with the decrease in temperature from 400 to 77 K, there is an improvement in AV, GFP, fT, and fMAX by ~7.43%, ~78.4%, ~78.38%, ~50.9%, respectively. It is also found AV gets degraded with the downscaling of Lg from 16 to 8 nm. However, the same resulted in the improvement of RF performance. From detailed analysis, it is further observed that the usage of high-k gate dielectrics (k=22) in JL-NSFET devices is not suitable due to the depreciation of analog/RF FOMs. Moreover, it is also noted that the improvement in analog/RF performance (ΔFoM = FoM(T=400) – FoM(T=100)) resulted from lowering the temperature can further be improved by downscaling of Lg and by using low-k gate dielectric.

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Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective

Cited by 16 publications

References 33 publications

Impact of temperature variation on linearity parameters of nanotube surrounding gate (NT‐SG) MOSFETs

Impact of temperature variation on linearity parameters of nanotube surrounding gate (NT‐SG) MOSFETs

Design and analysis of a double gate SiGe/Si tunnel FET with unique inner-gate engineering

Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node

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